RLC circuit

About: RLC circuit is a research topic. Over the lifetime, 14490 publications have been published within this topic receiving 142697 citations.

A CMOS Readout Circuit for SOI Resonant Accelerometer With 4- $\mu \rm g$ Bias Stability and 20- $ \mu\rm g/\sqrt{{\hbox{Hz}}}$ Resolution

Abstract: A fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 mug/radicHz resolution and 4 mug bias stability. The readout circuit draws 7 mA under 3.3-V supply.

Pressure sensor, pressure measuring apparatus, and pressure measurement system using them

Abstract: PROBLEM TO BE SOLVED: To provide a pressure measurement system using a pressure detection sensor that has a simple configuration and is inexpensive and a pressure measuring apparatus. SOLUTION: The pressure measurement system 1 comprises the pressure sensors 50a-50d and the pressure measuring apparatus 10. The pressure sensors 50a-50d are composed as a radio tag having a resonance circuit, where a resonance frequency changes depending on pressure. The pressure measuring apparatus 10 detects the resonance frequency of the resonance circuit and specifies the pressure of the radio tag, based on the detected resonance frequency, by transmitting or receiving radio waves to and from the pressure sensors 50a-50d. COPYRIGHT: (C)2004,JPO

$RLC$ Bridge Based on an Automated Synchronous Sampling System

Abstract: An RLC bridge based on an automated synchronous sampling system has been developed using commercially available high-resolution analog-to-digital and digital-to-analog converters. This bridge allows the comparison of any kind of impedance standards in the four-terminal-pair configuration at frequencies between 50 Hz and 20 kHz within a range from 1 Ω to 100 kΩ. An automatic balance of the bridge is carried out using a downhill simplex algorithm. Consistency checks have been realized by comparing resistance, inductance, and capacitance standards at different frequencies. The consistency of the measured voltage ratio is better than 20 μV/V over the whole frequency range and even smaller than 5 μV/V around 1 kHz. Finally, the results of the calibration of a 10-nF capacitance standard have been compared to those obtained using a commercial high-accuracy capacitance bridge. The difference is smaller than the commercial bridge specifications over the whole frequency range.

Modeling of power distribution systems for high-performance microprocessors

Abstract: This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information.

Clock recovery using an injection tuned resonant circuit

Abstract: A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In another embodiment, the nominal frequency of the LC tank circuit oscillator may be adjusted using a varactor or other voltage-controlled element in the LC tank circuit oscillator under the control of, e.g., the output of a separate PLL loop including another LC tank circuit oscillator. In one application, the injection tuned LC tank circuit forms a clock recovery cell using a clock signal embedded in a NRZ (Non Return to Zero) pseudo-random data stream. The slave oscillator in turn generates a recovered clock signal. In another application, a sub-harmonic clock signal in a 5.6 Gb/s NRZ (Non Return to Zero) 2 7 −1 pseudo-random data stream is used to injection lock a CMOS LC tank circuit to 2.8 GHz. The data stream is de-serialized into two 2.8 Gb/s data streams by a parallel combination of a positive and negative edge flip-flops (FF) clocked with alternate edges of this recovered clock.