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Showing papers on "Routing (electronic design automation) published in 1974"


Journal ArticleDOI
TL;DR: In this article, a dynamic programming method for routing pipe between two specified terminal points is developed and demonstrated, modified to meet requirements of practical piping runs, could be an important contribution toward a totally computerized piping arrangement method.
Abstract: A dynamic programming method for routing pipe between two specified terminal points is developed and demonstrated. This method, modified to meet requirements of practical piping runs, could be an important contribution toward a totally computerized piping arrangement method.

53 citations


Journal ArticleDOI
David W. Hightower1
TL;DR: In this paper, a survey of the literature on the interconnection problem is presented, including Pin Assignment, Layering, Ordering, Wire List Determination, Spanning Trees, Rectilinear Steiner Trees, and Wire Layout.
Abstract: This paper represents a fairly extensive survey of the literature on the interconnection problem. The topics covered are Pin Assignment, Layering, Ordering, Wire List Determination, Spanning Trees, Rectilinear Steiner Trees, and Wire Layout. In addition, several new ideas are presented which could provide for better wire layout. Algorithms are presented in a way that makes them easy to understand, hence easy to discuss and apply. Formal statement of the algorithms can be found in the references cited.

44 citations


Journal ArticleDOI

37 citations


Proceedings ArticleDOI
01 Jan 1974
TL;DR: By spreading the wires and increasing the crossover penalties, fewer crossings occur on each iteration until a crossing free layout is achieved.
Abstract: Wires are routed allowing crossings in the initial layout. By spreading the wires and increasing the crossover penalties, fewer crossings occur on each iteration until a crossing free layout is achieved.

27 citations


Journal ArticleDOI
TL;DR: Design automation applied to custom MOS circuit design significantly lowers the total design cost by shortening the design cycle, reducing labor, and allowing error free designs to be produced before being manufactured.
Abstract: Without sophisticated design automation techniques, the increasing complexity of custom MOS circuits requires long design cycles and large investments. Usually only a few parts of each type of custom MOS circuit are required, and the design cost becomes a significant portion of the cost of the manufactured parts. These facts prohibit many companies from using custom MOS circuits in their products. Design automation applied to custom MOS circuit design significantly lowers the total design cost by shortening the design cycle, reducing labor, and allowing error free designs to be produced before being manufactured. This makes possible the use of custom MOS circuits, even when only a few parts are required.

15 citations


Patent
16 Apr 1974
TL;DR: In this paper, the authors proposed a two-stage trunking scheme where each primary (A) switch has access to each secondary switch over an individual link, and the failure of any one link seriously affects accessibility as between incoming and outgoing paths of the network.
Abstract: In a two-stage switching network wherein each primary (A) switch has access to each secondary switch over an individual link, the failure of any one link seriously affects accessibility as between incoming and outgoing paths of the network. The present proposal is applicable where said paths are t.d.m. highways as in the digital switching subsystem (D.S.S.), and enables three requirements to be met (1) serial re-routing to avoid effect of an internal faulty link (2) avoidance of normal traffic blockages external to the two-stage network by use of second attempt connection, and (3) arbitrary access to and from digital loss pads providing R.O.M. translation of speech code level. The revised trunking of the two-stage network involves a "feed-back link" from the outgoing side of each B switch to the incoming side of the corresponding A switch. This enables any failed link to be avoided by 3 passes over the network; one of the passes being over any "feed-back link" except the two associated with switches of the failed link. Having provided the feed-back links primarily for evasion of faulty direct links, they are additionally used to include said digital loss pads. The t.d.m. channels in any feed-back link are subjected to the loss-pad facility or direct-switching of re-routed connections, as arbitrarily required, by suitable gating. In some circumstances time-sharing of one R.O.M. loss pad between two feed-back links is possible.

13 citations


Patent
02 Oct 1974
TL;DR: In this paper, a routing template assembly has been devised which is specifically adaptable for routing out slots of different widths in panels, boards and the like, such as in forming slots in side wall supports for insertion of shelf sections.
Abstract: A routing template assembly has been devised which is specifically adaptable for routing out slots of different widths in panels, boards and the like, such as for example, in forming slots in side wall supports for insertion of shelf sections. The template is characterized by a slotting guide which is adjustable in width depending upon the width of slot to be formed, adjustment being accomplished by setting the spacing between spaced parallel guide edges of the slotting guide to correspond to the desired width of the slot plus the diameter of the router guide bushing less the diameter of the routing bit.

11 citations


Proceedings ArticleDOI
01 Jan 1974
TL;DR: Engineering Data Management System - EDMS is developed so as to be open-ended general purpose DA system which can meet with the future innovation of the technology.
Abstract: The current technology lets a DA system handle the data on various design levels such that pure logical, logical and physical and pure physical information are mixedly used on a PCB design.The design process has not been uniformly carried out, such that the simulation of digital system, the routing and a PCB and a unit design has been carried out at the same time, and made the operation and the management be more difficult and complicated. Therefore, only extention of traditional DA systems tends to be difficult to cope with these situations.We have studied these problems and developed Engineering Data Management System - EDMS - so as to be open-ended general purpose DA system which can meet with the future innovation of the technology.

8 citations


Proceedings ArticleDOI
01 Jan 1974
TL;DR: Force-directed placement algorithms are experimentally compared using several sample problems and significant differences are noted in the computational efficiency of the algorithms, and in the relationship of the placement solution to the routability of the resulting board.
Abstract: Force-directed placement algorithms are experimentally compared using several sample problems. Significant differences are noted in the computational efficiency of the algorithms, and in the relationship of the placement solution to the routability of the resulting board.

7 citations


Journal ArticleDOI
TL;DR: This paper will discuss combinatorial uniform shift networks that can shift a binary word a variable number of bit positions.
Abstract: This paper will discuss combinatorial uniform shift networks that can shift a binary word a variable number of bit positions. Typical arithmetic applications are for prenormalization or alignment of one of the mantissas in floating point addition, postnormalization of the mantissa in any normalized floating point operation, or for one or more bits of shifting in multiply and divide. Other applications include • packing and unpacking of fields stored in memory either within the processor itself or as part of a separate unit between the processor and the memory (such a unit, called a "field isolation unit," is described by DeSantis, et al1); • isolation of fields of a word in the instruction decoding and break-apart done during emulation of various machines; and • variable-length routing of words between all processors in an array computer by transposing the processor/data word matrix, shifting by the routing distance, and transposing the resultant data word/processor matrix back, as described by Semmelhaack.2

6 citations


Book ChapterDOI
20 Aug 1974
TL;DR: The number of cross-bar switches required to form a programmable data routing network [PDRN] for interconnecting multiple computing elements [CE]'s is reduced and all existing methods used for finding maximum flow in transport networks or for finding completely matched sets in bipartite graphs can be used to solve the middle block assignment problem in a PDRN.
Abstract: This paper deals with the reduction of the number of cross-bar switches required to form a programmable data routing network [PDRN] for interconnecting multiple computing elements [CE]'s and the programming of such networks. The reduction is done by using triangular PDRN's [TPDRN's] to form a multistage network, conditioned on an a priori knowledge of interconnections. The programmability of the proposed PDRN's is specified by the design and the implementation of a route finding algorithm in a multistage PDRN. It is also found that all existing methods used for finding maximum flow in transport networks or used for finding completely matched sets [CMS] in bipartite graphs can be used to solve the middle block assignment problem in a PDRN. A set-up algorithm for a particular type of memory cell in a TPDRN is developed. The worst case propagation delays in the proposed PDRN's are also analyzed. Note that the proposed PDRN's become more advantageous when the number of CE's is large (more than 100). The applications of the proposed PDRN's may include multiprocessors, single and multiple access memory modules, dynamic allocations of memories, dynamic digital computers, digital differential analyzers, automatic patching of analog/hybrid computers with some modifications etc.

Proceedings ArticleDOI
01 Jan 1974
TL;DR: A complete, computerized artwork processing system for Integrated circuits and printed circuit boards includes digitizers, plotters, a design rule checker, and a pastern generator command program.
Abstract: A complete, computerized artwork processing system for Integrated circuits and printed circuit boards includes digitizers, plotters, a design rule checker, and a pastern generator command program. Its success depends on simplicity, consistency and technology independence.


Proceedings ArticleDOI
01 Jan 1974
TL;DR: BAAR, a program to route conductor paths on printed-wiring boards, is based upon the Moore-Lee algorithm and incorporates an effective path-cost function and a programmability feature, and is producing results which are very good.
Abstract: This paper discusses BAAR, a program to route conductor paths on printed-wiring boards. It is based upon the Moore-Lee algorithm1,2 and incorporates an effective path-cost function and a programmability feature. It is written in ALGOL for the Burroughs B6700 and is producing results which are very good in both of two respects: the quality of individual paths is comparable to what a human would produce, and completion rates are very high.The particular path-cost function used is inherently capable of yielding much better paths than a simple Manhattan-distance function, but the principal advantage of the program lies in the feature whereby a user may design a routing strategy for a particular board topography and then “program” the router to execute that strategy. The result is an algorithm which is remarkably simple, without the usual host of preprocessors, postprocessors, and special-case routines, while at the same time constituting a tool of considerable power and flexibility.

Proceedings ArticleDOI
01 Jan 1974
TL;DR: This paper presents a Computer Aided Design (CAD) system which is intended for practical use in master-slice LSI design and testing and includes five sub-systems; PLACEMENT, ROUTing, IMPROVE, ARTWORK, and TEST GENERATION.
Abstract: This paper presents a Computer Aided Design (CAD) system which is intended for practical use in master-slice LSI design and testing. This system includes five sub-systems; PLACEMENT, ROUTING, IMPROVE, ARTWORK, and TEST GENERATION.

01 Jan 1974
TL;DR: This paper shows how to dimension store andward networks with alternate rout taking into account the special properties of 6verflow traffic, and shows the good accordance between imulated and calculated traffic values.
Abstract: I~ modern data networ~variable routing strategles allow to take into account the instantaneous traffic situation of the network. Traffics offered to a direct "primary" route can be described realistically by means of Poisson traffic and therefore all characteristic traffic values can be determined by means of well known formulas. However, traffics overflowin~ from a primary to a secondary route nos · se~squlte other stochastic properties than POlsson traffic . This paper shows. how to dimension store and ~orward networks with alternate rout -Lng taking lnto account the special properties of 6verflow traffic. Artificial traffic trials show the good accordance between s imulated and calculated traffic values.

Journal ArticleDOI
TL;DR: Using the manhattan metric, a heuristic procedure is described which provides minimum length placements on two-sided printed circuit boards consistent with the requirements of PC board designers.

Journal ArticleDOI
TL;DR: An algorithm is presented for obtaining a suboptimum covering with considerable efficiency in computation and overall data manipulation for improved storage procedures for route generation for demand actuated systems.
Abstract: The use of improved storage procedures for route generation for demand actuated systems is necessary for practical implementation of many routing systems. Neighborhood Storage is a method of storing the system information which requires a covering to be generated for a number of sets of points which are generated by the method. The set covering problem is important to the overall practical implementation of the method. The method requires M coverings to be generated for each application. Thus, computational efficiency is of considerable importance in obtaining the required coverings. The problem is defined and formulated as a set covering problem. Solutions are carried out for a number of examples and the results for the optimum covering are reported. An algorithm is then presented for obtaining a suboptimum covering with considerable efficiency in computation and overall data manipulation. The example results are also included. The algorithm presented is applicable to any (V;A,B) modeled in R2.

Proceedings ArticleDOI
01 Jan 1974
TL;DR: LSI chip area and design time, reduced by improving automatic layout programs and by combining them with interactive refining techniques, will be discussed.
Abstract: LSI chip area and design time, reduced by improving automatic layout programs and by combining them with interactive refining techniques, will be discussed Packing density of layouts has been found to be at least equal to that of manual designs


Proceedings ArticleDOI
01 Jan 1974
TL;DR: The task of routing large multilayer printed wiring boards is a tedious, time-consuming and error-prone procedure if done manually, so an interactive graphics system has been built to aid this process.
Abstract: The task of routing large multilayer printed wiring boards (most commonly back-planes) is a tedious, time-consuming and error-prone procedure if done manually. The size and general uniformity of the board plus the large number of connections makes the probability of error very high.To aid this process, an interactive graphics system has been built. Because of the specialized nature of the problem, it was both necessary and possible to build the program in such a way as to allow the interactive graphics terminal to be a true design station instead of just an efficient data capture station.

01 Dec 1974
TL;DR: App Appendix A takes the integer programming formulation of Dantzig, Fulkerson, and Johnson which is relaxed to a linear program and a column generation scheme found for its dual.
Abstract: The first report provides the background for routing solid waste collection vehicles. Problems encountered with existing methods and possible solutions are given. Appendixes A and B are solutions to two classic routing problems. Appendix A takes the integer programming formulation of Dantzig, Fulkerson, and Johnson which is relaxed to a linear program and a column generation scheme found for its dual. Appendix B (separately bound) is a study applying network theory to the problem of routing a solid waste collection vehicle through a street network. The problem can be described mathematically as a linear program whose optimal solution is guaranteed to be integer.



01 Sep 1974
TL;DR: The factors, events and situations contributing to bottlenecks in message processing are identified as fully as possible within the constraints of time and information availability.
Abstract: : This thesis represents the results of a study of the U. S. Naval Processing and Routing System (NAVCOMPARS). The system's development from preconception to present is described herein as well as a description of its hardware and software components. Additionally, the Local Digital Message Exchange (LDMX), is likewise described. The purpose of this thesis is to identify bottlenecks in message flow through NAVCOMPARS5 In this attempt, the system was simulated in a functional manner by computer and various input distributions were applied. By so doing, the factors, events and situations contributing to bottlenecks in message processing are identified as fully as possible within the constraints of time and information availability. (Author)

01 Jun 1974
TL;DR: In this paper, the authors presented a global minimum solution for a 10,000-node cost minimization problem, which can be viewed as a discretized optimal control problem and can be applied to situations where there may be errors in the control that necessitate a closed-loop control.
Abstract: If a set of N points or nodes with a nonnegative cost associated with each ordered pair is known, it is desired to find a path from one given node to another given node which minimizes the cost sum. An algorithm is presented which yields a global minimum solution after at most N - 1 iterations or on a typical large third-generation computer, after 1 hour of computation time for a 10,000-node problem. The rapid-access data storage capacity demanded by the algorithm is approximately 3N words for costs read in from slow-access storage or 2N words for calculable costs. The time-storage requirements of the algorithm known to the authors. When the problem is viewed as a discretized optimal control problem, after N-1 iterations, an optimal control or node transition is established for each of the N nodes or states; thus, the algorithm can be applied to situations were there may be errors in the control that necessitate a closed loop control that necessitate a closed loop control philosophy.

Proceedings ArticleDOI
01 Jan 1974
TL;DR: An integrated systems approach has been used to formulate a model for the analysis of routes and the routing of vehicles that utilizes the network to optimally route a vehicle from a specified starting point to a given destination.
Abstract: An integrated systems approach has been used to formulate a model for the analysis of routes and the routing of vehicles. The essential data to describe the available routes are stored in the form of a network; the directional relationships and the relative location of the routes are established with the aid of a grid. The GASP II simulator has been used to develop the model. The model utilizes the network to optimally route a vehicle from a specified starting point to a given destination; it employs a variety of techniques which includes dynamic programming, branch and bound, and simulation.