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Showing papers on "Routing (electronic design automation) published in 1976"


Proceedings ArticleDOI
David N. Deutsch1
28 Jun 1976
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Abstract: This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.

364 citations


Proceedings ArticleDOI
25 Oct 1976
TL;DR: Several polynomial time approximation algorithms for some NP-complete routing problems are presented, and the worst-case ratios of the cost of the obtained route to that of an optimal are determined.
Abstract: Several polynomial time approximation algorithms for some NP-complete routing problems are presented, and the worst-case ratios of the cost of the obtained route to that of an optimal are determined. A mixed-strategy heuristic with a bound of 9/5 is presented for the Stacker-Crane problem (a modified Traveling Salesman problem). A tour-splitting heuristic is given for k-person variants of the Traveling Salesman problem, the Chinese Postman problem, and the Stacker-Crane problem, for which a minimax solution is sought. This heuristic has a bound of e + 1 - 1/k, where e is the bound for the corresponding 1-person algorithm.

315 citations


Proceedings ArticleDOI
03 May 1976
TL;DR: Two algorithms for sorting n2 elements on an n×n mesh-connected processor array that require 0(n) routing and comparison steps are presented and are shown to be optimal in time within small constant factors.
Abstract: Two algorithms for sorting n2 elements on an n×n mesh-connected processor array that require 0(n) routing and comparison steps are presented. The best previous algorithms take time 0(n log n). Our algorithms are shown to be optimal in time within small constant factors.

127 citations


Journal ArticleDOI
TL;DR: In this article, suboptimal algorithms are advanced for routing single nets subject to the minimum length constraint and multinets subject to minimum length and maximum allowable channel capacity constraints, using known results in Steiner's problem.
Abstract: Using known results in Steiner's problem, suboptimal algorithms are advanced for routing single nets subject to the minimum length constraint and multinets subject to the minimum length and maximum allowable channel capacity constraints. Implementation of the algorithm on a large number of randomly generated examples indicates feasibility of fast CPU execution time and good quality of solution in comparison with other existing algorithms.

89 citations


Journal ArticleDOI
TL;DR: An easily implementable sufficient condition on the routability of a net list over a single row of nodes is presented and the solution is an improvement over the worst-case prediction of So.
Abstract: The multilayer routing problem is introduced and its relation to the single-row single-layer routing problem is illustrated [1], [2]. An easily implementable sufficient condition on the routability of a net list over a single row of nodes is presented. The solution is given by a constructive forward marching procedure and the result is an improvement over the worst-case prediction of So [1]. The implementation algorithm is programmed on CDC 6400 computer. The nature of the optimum criterion relating to single-row routability is investigated and a necessary and sufficient condition is given to characterize the nature of optimality. Some necessary conditions are also presented which can be used to evaluate the sufficient condition and served as a lower bound for the channel capacity in the routing problem. The more general routing problem is illustrated and possible future research directions are discussed.

78 citations


Journal ArticleDOI
Jeffrey H. Hoel1
TL;DR: This paper discusses some variations of Lee's algorithm which can be used in certain contexts to improve its efficiency and shows that by storing frontier cells in an array of stacks rather than a single list, costly searching operations can be eliminated without significantly increasing storage requirements.
Abstract: Lee's algorithm is a pathfinding algorithm, which is often used in computer-aided design systems to route wires on printed circuit boards. This paper discusses some variations of Lee's algorithm which can be used in certain contexts to improve its efficiency. First, it is shown that, by storing frontier cells in an array of stacks rather than a single list, costly searching operations can be eliminated without significantly increasing storage requirements. Second, it is shown that if each path's cost is the sum of the weights of its cells then retrace codes can be assigned to cells as soon as they are reached rather than when they are expanded. Third, it is shown that if the additional restriction is made that each cell's weight is not a function of the state of any nonneighbor cell, then an encoding scheme requiring only two bits/cell can be used for both rectangular and hexagonal grids.

77 citations


Proceedings ArticleDOI
28 Jun 1976
TL;DR: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design.
Abstract: LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc.In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.

71 citations


01 Jan 1976
TL;DR: The specifications, analysis and evaluation of some routing and topology design procedures for large store and forward packet switched computer communication networks rely on a hierarchical clustering of the network nodes.
Abstract: : This research deals with the specification, analysis and evaluation of some routing and topology design procedures for large store and forward packet switched computer communication networks. The procedures studied are an extension of present techniques and rely on a hierarchical clustering of the network nodes.

39 citations


Patent
21 Apr 1976
TL;DR: In this article, a general digital message network for short address-coded telegrams having plural switching stations is presented. But the routing word associated with the outgoing line of the output store is stored in such a way that upon correspondence of routing word in one of the fixed value stores with the routing words at a specific location of the address of the telegram in the associated output store, this telegram is transmittable onto the output line thereof.
Abstract: A general digital message network for short address-coded telegrams having plural switching stations. In each switching station the outputs of the input stores are each connected to one of the inputs of a multiplexer. The inputs of the output stores are connected to the output of the multiplexer and the output stores are each connected to a comparator circuit with a fixed value store in which the routing word associated with the outgoing line of the output store is stored, in such a way that upon correspondence of the routing word in one of the fixed value stores with the routing word at a specific location of the address of the telegram in the associated output store, this telegram is transmittable onto the output line thereof.

37 citations


01 Jun 1976
TL;DR: In this paper, a distributed algorithm for constructing minimal spanning trees in computer-communication networks is presented, which can be executed concurrently and asynchronously by the different computers of the network.
Abstract: This paper presents a distributed algorithm for constructing minimal spanning trees in computer-communication networks. The algorithm can be executed concurrently and asynchronously by the different computers of the network. This algorithm is also suitable for constructing minimal spanning trees using a multiprocessor computer system. There are many reasons for constructing minimal spanning trees in computer-communication networks since minimal spanning tree routing is useful in distributed operating systems for performing broadcast, in adaptive routing algorithms for transmitting delay estimates, and in other networks like the Packet Radio Network.

35 citations


Proceedings ArticleDOI
28 Jun 1976
TL;DR: An automatic string placement program used to reorder cells in polycell rows such that channel routing in the adjacent channels is not blocked by cyclic constraints, and the program needs fewer routing tracks.
Abstract: This paper describes an automatic string placement program used to reorder cells in polycell rows such that channel routing in the adjacent channels (a) is not blocked by cyclic constraints, and (b) needs fewer routing tracks. The program utilizes cell reflections and pairwise neighbor exchanges, simultaneously monitoring both the channels immediately above and below the row being reordered. Reductions of 25% in the number of required routing tracks are commonly obtained.

Proceedings Article
01 Jan 1976
TL;DR: Several polynomial time approximation algorithms for some $NP$-complete routing problems are presented, and the worst-case ratios of the cost of the obtained route to that of an optimal are determined.
Abstract: Several polynomial time approximation algorithms for some $NP$-complete routing problems are presented, and the worst-case ratios of the cost of the obtained route to that of an optimal are determined. A mixed-strategy heuristic with a bound of 9/5 is presented for the stacker-crane problem (a modified traveling salesman problem). A tour-splitting heuristic is given for k-person variants of the traveling salesman problem, the Chinese postman problem, and the stacker-crane problem, for which a minimax solution is sought. This heuristic has a bound of $e + 1 - 1/k$, where e is the bound for the corresponding 1-person algorithm.

Journal ArticleDOI
01 Jan 1976-Networks
TL;DR: The RPP, TSP, and GRP a r e a l l polynomial complete rout ing problems, and why they requi re branch and bound (subtour e l imina t ion) a lgori thms, as well as the theorem presented.
Abstract: The no te , \"On General Routing Problems\" by J. K. Lenstra and A . H . G . Rinnooy Kan [ I ] , c o r r e c t s two e r r o r s i n recent papers by the author [2,31 on General Routing Problems, b u t it tends t o obscure the r e a l i s sue i n determining the complexity, or d i f f i c u l t y , i n solving ac tua l rou t ing problems. The RPP, TSP, and GRP a r e a l l polynomial complete rout ing problems, and t h a t i s p rec i se ly why they requi re branch and bound (subtour e l imina t ion) a lgori thms, a s given i n [ 2 1 , which a re not polynomial bounded. For such problems, an important approach i s t o reduce t he complexity of the problem a s much as poss ib le . The complexity of G R P problems depends not only on the number of odd nodes and required nodes (which may, f o r example, be t h e same f o r a TSP and CPP) bu t more important ly , on the number of disconnected components i n the problem ( the TSP has N while the CPP has only one ) . I t i s recommended i n [21 t h a t , as f a r as poss ib l e , required nodes be converted t o required a rc s because t h a t reduces the number of disconnected components i n the problem (because every required node i s a disconnected component, while required a rc s tend t o be connec ted) . The theorem presented i n 111 , t h a t t h e RPP i s polynomial complete, i s t r u e b u t misleading. The RPP i s fundament a l l y more d i f f i c u l t than the CPP because it has disconnected components. The theorem i s obvious, s ince any TSP can be conver ted t o an equivalent RPP by expanding any TSP node j t o a required arc ( j , j ') where j ' i s an a r t i f i c i a l dupl ica te of j . Of course, t h i s t ransformation from TSP t o RPP i s of no b e n e f i t , except a 2-matching problem on N nodes i s converted t o an equivalent 1-matching problem on 2 N nodes. On the o the r hand, an RPP with only 2 disconnected components i s not much more d i f f i c u l t t o so lve than a CPP ( a t most one branch i n the branch and bound procedure i s r equ i r ed ) . I n complexity o r d i f f i c u l t y , the RPP is somewhere between t h e CPP and t h e TSP, where the c r i t i c a l f a c t o r i s the number of disconnected components.

Journal ArticleDOI
TL;DR: In this paper, the authors discuss the General Routing Problem approach to solving large scale routing problems and propose a heuristic to produce optimum and near optimum solutions quickly. But, the heuristics are not suitable for large-scale networks.
Abstract: This paper discusses the General Routing Problem approach to solving large scale routing problems. The General Routing Problem on network G = N; A requires finding the minimum cost cycle that visits every node in subset Q ⊆ N and that traverses every arc in a subset R ⊆ A. Utilizing special problem characteristics and the structure of real transportation networks, large reduction in effective problem size and complexity can often be made. This permits a very effective heuristic to produce optimum and near optimum solutions quickly.

Proceedings ArticleDOI
28 Jun 1976
TL;DR: A block placement program and a routing program for inter-block connection of master-slice LSI's are described, which reduces the total expected wire length, by iterative improvements of block placement and gate assignment to blocks.
Abstract: A block placement program and a routing program for inter-block connection of master-slice LSI's are described. The placement program reduces the total expected wire length, by iterative improvements of block placement and gate assignment to blocks. The routing program employs Lee's algorithm basically, and modifications have been made to increase wirability and reduce computer time. The results of applying these programs to several types of LSI's are presented.

01 Mar 1976
TL;DR: The synthesis of optimal reliable (invulnerable) topological structures for message-switching communication networks is considered, and complete networks are shown to be optimal if the resulting lines have a high average line utilization value.
Abstract: The synthesis of optimal reliable (invulnerable) topological structures for message-switching communication networks is considered. The connectivity of the underlying graphs is used as a measure of the network invulnerability. The maximal average message delay value is utilized as the network delay measure. Simultaneously with choosing the topological structure, optimal line capacities are assigned. Therefore, the performance measure of a given network structure is chosen to be given by its delay-capacity product function, incorporating the product of the prescribed network maximal delay value and the associated minimal overall line capacity value. The latter involves a distance-independent link cost function incorporating the line capacity. A general routing discipline is used to account for dynamic updating of fixed routing procedures, needed to accomodate terminal traffic flow fluctuations. n -node k -connected graphs yielding networks with minimal delaycapacity product functions are characterized and realized. Complete networks (utilizing direct dedicated lines) are shown to be optimal if the resulting lines have a high average line utilization value. Otherwise (under appropriate symmetry conditions on the network traffic matrix), the optimal message-switching reliable network structures are characterized by a family of graphs of diameter two. The latter thus allow between any pair of nodes a route which is either a direct line or contains a single intermediate node. Also noted is a family of k -connected networks, for which the delay-capacity product function is not increased by more than twice upon the failure of (k-1) or less nodes or lines.

Patent
Jr. Carl Jerome May1
26 May 1976
TL;DR: In this paper, a reference source of uniformly spaced pulses is coupled to the input of a smooth sequence generator (SSG) which is capable of dividing the reference pulse sequence by any proper, predetermined, rational fraction (e.g., 193/512).
Abstract: A reference source of uniformly spaced pulses is coupled to the input of a smooth sequence generator (SSG) which is capable of dividing the reference pulse sequence by any proper, predetermined, rational fraction (e.g., 193/512). The SSG comprises a plurality of routing circuits connected in tandem. Each routing circuit has a first and second output and a control terminal which serves to route a pulse presented at the routing circuit input to either said first or second output. The first output of each routing circuit is connected to the next tandem-connected routing circuit. A feedback connection from the first output of each routing circuit to the control terminal of the preceding routing circuit serves to control the routing of a pulse presented to the input of the latter. A synchronization circuit is coupled to the output of said reference source, via a divider circuit, and to the first output of the last tandem-connected routing circuit. The sync circuit output is delivered to the control terminal of said last routing circuit to constrain (i.e., lock) the frequency, and preferably even the phase, of the SSG source.

Proceedings ArticleDOI
28 Jun 1976
TL;DR: A new routing program that partitions a printed circuit board into regions called saturated zones and is subsequently merged by routing into larger and larger saturated zones until the final combination yields a routing for the entire board.
Abstract: This paper discusses a new routing program. The program initially partitions a printed circuit board into regions called saturated zones. These saturated zones are subsequently merged by routing into larger and larger saturated zones until the final combination yields a routing for the entire board. The algorithm gains efficiency and effectiveness from the fact that restricted sets of wires are considered in parallel.

Proceedings ArticleDOI
28 Jun 1976
TL;DR: This paper describes a printed circuit routing program based on a cellular least-cost path finding algorithm that uses four bits of random access storage per cell and provides a mechanism for programming the path-cost function to model a variety of physical constraints.
Abstract: This paper describes a printed circuit routing program based on a cellular least-cost path finding algorithm. The program uses four bits of random access storage per cell and provides a mechanism for programming the path-cost function to model a variety of physical constraints.

Patent
09 Dec 1976
TL;DR: In this paper, a MOST is used for channel routing in which the source (1) drain and gate (2) are of comb and zigzag shapes as appropriate and mounted on a substrate with implanted conducting elements (7) and covered with a protective layer (9) so that a compact layout with a relatively high channel length to width ratio is achieved.
Abstract: The basic element used is a MOST, of which the source (1) drain (2) and gate (3) are of comb and zigzag shapes as appropriate and are mounted on a substrate (6) with implanted conducting elements (7) and covered with a protective layer (9) so that a compact layout with a relatively high channel length to width ratio is achieved. The interelectrode capacitances are reduced by the addition of two further layers (11, 13) above the protective layer, one (11) of conducting material which is held at a constant potential. Matrices of these elements for channel routing centres can be constructed with suitably constructed connectors.

Proceedings ArticleDOI
28 Jun 1976
TL;DR: Design automation of electronic systems is generally separated into a number of distinct areas of effort, while this separation may not be complete or entirely accurate.
Abstract: Design automation of electronic systems is generally separated into a number of distinct areas of effort. Breuer [1] has divided design automation into the areas of logic synthesis, gate simulation, partitioning, placement, routing, and fault detection and diagnosis. While this separation may not be complete or entirely accurate, these functions generally must be performed.

Proceedings ArticleDOI
01 Dec 1976
TL;DR: This paper describes an approach for determining the feedback solution when all the inputs to the network are constant in time, and finds that the approach has some appealing simplifying properties for networks which have only a single destination.
Abstract: In [1] Segall introduces a state space model and associated optimal control problem for dynamic routing of messages in a data communication network. The optimal control problem is completely linear with state and control variable inequality constraints. In this paper we report on progress in solving the optimal control problem for a feed-back solution. In particular, we describe an approach for determining the feedback solution when all the inputs to the network are constant in time. For networks which have only a single destination (multiple sources) it is found that the approach has some appealing simplifying properties. The details underlying the approach described here are presented in Moss [2].



Proceedings ArticleDOI
28 Jun 1976
TL;DR: The techniques used within the company are outlined and some of the procedural advancements are indicated, and the reasons for their introduction are indicated.
Abstract: The introduction of electronic processor controlled switching systems has led to a re-appraisal of the methods of designing printed wiring boards to cope with the sheer numbers of designs required and their increasing complexity. The Company's policy is normally to realise the equipment on double sided printed wiring boards (pwb) containing a maximum of 80 integrated circuits per board plus discrete components. (Figs. 1 and 2)PWB requirements are frequently changing as new techniques and processes are introduced and therefore methods of improving pwb layout and artwork preparation are continually under investigation.This paper outlines the techniques used within the company and indicates some of the procedural advancements, and the reasons for their introduction.

Journal ArticleDOI
TL;DR: This paper describes straightforward techniques for layout improvement that are routing algorithm independent and simple to implement.
Abstract: Automatic routing programs produce layouts which contain features that could be improved. This paper describes straightforward techniques for layout improvement that are routing algorithm independent.

Proceedings ArticleDOI
28 Jun 1976
TL;DR: In an experiment at Raytheon, an experiment was undertaken to increase the percentage of signals routed (in a batch router), the improvement technique consisted of modifying the order and manner in which connections were routed.
Abstract: Many attempts have been made to create better routers by developing new algorithms or modifying existing ones, the results of which have been published (sometimes).At Raytheon, an experiment was undertaken to increase the percentage of signals routed (in a batch router). The improvement technique consisted of modifying the order and manner in which connections were routed. This was accomplished by splitting the signal networks into parts, and using different rules for routing the different parts.


Proceedings ArticleDOI
01 Sep 1976
TL;DR: A new computer program CALMOS has been developed for the automatic layout of MOS-LSI circuits and provides an automatic 100% routing with emphasis on the minimization of the interconnection area.
Abstract: A new computer program CALMOS has been developed for the automatic layout of MOS-LSI circuits. It runs on a minicomputer and provides an automatic 100% routing with emphasis on the minimization of the interconnection area.

Proceedings ArticleDOI
01 Dec 1976
TL;DR: This talk focuses on the application of analytical techniques to the study of two critical and interrelated control problems in data communication networks, respectively, congestion control and adaptive, routing.
Abstract: In this talk we focus on the application of analytical techniques to the study of two critical and interrelated control problems in data communication networks. These are, respectively, congestion control and adaptive, routing. Both of these problem areas may be subsumed under the general question of optimum resource allocation in data networks. In essence the basic problem is that of appropriately allocating the system resources (for example, nodal buffers and channel capacity) so as to maintain a desired throughput in the network at a given cost, with as small a time delay as possible. Other criteria exist as well, and some of these may in fact be mutually incompatible.