Showing papers on "Routing (electronic design automation) published in 1979"

Complexity Of Vehicle Routing And Scheduling Problems

Abstract: The complexity of a class of vehicle routing and scheduling problems is investigated. We review known NP-hardness results and compile the results on the worst-case performance of approximation algorithms. Some directions for future research are suggested. The presentation is based on two discussion sessions during the Workshop to Investigate Future Directions in Routing and Scheduling of Vehicles and Crews, held at the University of Maryland at College Park from June 4 to June 6, 1979.

A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation

Abstract: A new placement algorithm for general cell assemblies is presented which combines the ideas of polar graph representation and min-cut placement. First a detailed description of the initial placement procedure is given, then the various methods for placement improvement (rotation, squeezing, reflecting) and global routing are discussed. A sample circuit is used to demonstrate the performance of the algorithms. Results are shown to compare favourably with manually achieved solutions.

An assignment routing problem

Abstract: This paper examines a routing design problem in which the objective is to assign customer demand points to days of the week in order to solve the resulting node routing problems over the entire week most effectively. The emphasis is on obtaining approximate solutions for this type of combinatorial problem. Several heuristics are developed and tested on a large scale refuse collection problem. Computational results, as well as a discussion of expected benefits, are presented.

On optimum single-row routing

Abstract: The problem of single-row routing represents the backbone of the problem of general routing of multilayer printed circuit boards. In this paper, the necessary and sufficient condition for optimum single-row routing is obtained. By optimum routing we mean minimumm street congestion. A novel formulation is introduced. Examples are given to illustrate how optimum routings are derived. A graph theory interpretation of the condition is also given.

Alternate routing for a telephone system

Abstract: An alternate routing scheme for a telephone system wherein a plurality of switching offices are grouped into a cluster, with each switching office in the cluster having direct trunk lines to all the other switching offices in its cluster. This allows each switching office in the cluster to serve the dual function both of an originating (or terminating) office and of a tandeming office for its own cluster. Suitable equipment monitors the busy status of all the switching offices in the cluster, and determines a most likely alternate routing scheme for each switching office. The alternate routing scheme for each particular switching office is stored at that particular office and is periodically updated, by suitable equipment, so as to account for changes in the busy status of the other switching offices and trunk lines in the cluster.

Placement Algorithms for Arbitrarily Shaped Blocks

Abstract: New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits. Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of interconnected rectangular blocks of arbitrary size and shape such that the area occupied by the blocks and their interconnections is minimal. Constructive initial placement and iterative improvement algorithms are presented.

Automatic printed circuit dimensioning, routing and inspecting apparatus

Abstract: An automatic apparatus is employed to recognize certain features on a printed circuit board and display that information on a screen so that an operator can create machine instructions for operations at those specific locations. Initially a printed circuit mask is placed on an X-Y table. A scanner automatically passes over the mask and searches for holes or other specific features. An interface system is employed to interface the scanner with a conventional computer. Several operations are employed to positively identify and locate a hole by size. Hole data is then checked to throw out duplicate information. Once the hole sizes are identified the information may be placed on a CRT screen. A machine operator then uses a stylus or other means to place machine instructions into memory at the location of the displayed features. The device may also be used to provide instructions to a routing machine or to compare a drilled printed circuit board with a previously scanned master negative.

Charge-routing networks

Abstract: The fundamental techniques for charge manipulation achievable with MOS charge-coupling technology include storage, transfer, splitting, combining, insertion, and extraction. We idealize and generalize these operations to define a general class of networks for discrete-time linear filtering. A p-phase charge-routing network (CRN) consists of a collection of storage cells divided into p subgroups and a routing procedure controlled by a p-phase clock. During a particular clock phase, charge is routed from a particular subgroup of storage cells into another subgroup. In this manner charge is routed successively through each subgroup of cells and a periodically time-varying linear discrete-time network is defined by specifying matrices of weight values associated with the routing procedure. Analysis of a p -phase CRN yields a reduced system of linear time-invariant dynamic state equations convenient for signal-processing studies. Necessary and sufficient conditions on such a system of state equations are given for realizability as a p -phase CRN. The varied structures attainable with CRN's can realize infinite inpulse-response filter transfer functions. However, certain fundamental restrictions exist on the class of transfer functions realizable with CRN's. In particular, we show the existence of forbidden zones within the unit circle in the z-plane, where poles (or natural modes) of a CRN cannot occur. A parallel can be drawn between classical RC networks and charge-routing networks. Both types of networks have substantial restrictions on the class of filters they can by themselves realize. For RC networks, we know the limitations can be overcome by the addition of another component (inductance or operational amplifier). A similar potential may exist for CRN's. This paper provides a foundation for a general theory that could offer realizability conditions and sythesis procedures for discrete-time filtering via charge routing networks.

Global Router

Abstract: The paper describes a new router which develops all connections simultaneously. Routes do not exist as lines, but rather as connected irregularly shaped areas which grow and retract in an amoeba-like manner. It is as if some routes are being rerouted, but it is all done at once. Because the cell map is scanned sequentially, the data handling and storage is vastly simplified.

Three-stage multiconnection networks which are nonblocking in the wide sense

Abstract: A multiconnection network deals with the connections of pairs {(X, Y)} where X is a subset of the input terminals and Y is a subset of the output terminals. We study the conditions under which a three-stage Clos network is nonblocking for such connections. We show that the number of middle switches needed for nonblocking depends on the routing strategy. Therefore the networks satisfying the conditions are networks nonblocking in the wide sense. We also derive formulas for computing the minimum numbers of crosspoints required by such networks.

Approximations of Queue Dynamics and Their Application to Adaptive Routing in Computer Communication Networks

Abstract: Various adaptive algorithms have been proposed for routing, flow and congestion control in packet-switched computer communication networks. In most of them, information on queue lengths, or equivalently, time delays, at various points in the network is required for proper adaptation. Since up-to-date information is not always available, these quantities must be estimated based on prior information. This paper presents approximations for the dynamic behavior of the M/M/1 queue which is used to yield the desired estimates of queue lengths. Based on the assumption of finite (but arbitrarily large) storage, a closed form expression for the evolution in time of the queue length distribution is obtained. From this expression various approximations for estimated queue length are extracted. A simple expression for the "relaxation time" of the queue is also deduced as a function of utilization factor and service time. The approximations are applied to a simple adaptive routing example in which packets are routed along the transmission path having the shortest estimated queue, based on delayed information.

The Minimum Width Routing of a 2-Row 2-Layer Polycell-Layout

Abstract: This paper presents a new routing principle that leads to an algorithm to realize the minimum width of the 2-layer channel area between two rows of terminals to be interconnected. Besides the theoretical results, practically applicable routing algorithms based on our principle are developed.

Via assignment problem in multilayer printed circuit board

Abstract: In the routing of a multilayer printed circuit board an important phase is the via assignments. In this paper, the via assignment problem is given a graph theoretic formulation. Some related optimization problems are proven to belong to a particular class of hard combinatorial problem: the class of nondeterministic polynomial (NP)-complete problems. This result suggests that the only way to solve efficiently the optimization problems is to introduce heuristic algorithms. Hence, some heuristic algorithms a proposed and their performances are evaluated.

An algorithm for the via assignment problem in multilayer backboard wiring

Abstract: The multilayer routing approach first introduced by So is one of the most promising to the layout especially for large-scale multilayer backboards. Associated with this, the problem of which vias are to be assigned for each signal net is an important factor to reduce the number of via columns, and hence the wiring area of a backboard. In this paper, we first formulate an optimization portion of this problem and consider its inherent computational complexity to reveal that this problem belongs to the P -complete class. We then propose a heuristic polynomial-time algorithm to this problem.

MIRAGE - A Simple-Model Routing Program for the Hierarchical Layout Design of IC Masks

Abstract: A simple-model routing program -MIRAGE- which is used in the hierarchical layout design of large scale IC masks is described together with some experimental results. By applying it hierarchically several times, satisfactory results can generally be obtained.

A Hierarchical Placement Procedure with a Simple Blocking Scheme

Abstract: The outline of a hierarchical placement procedure utilizing a simple blocking scheme is described with the results of the application to the DSA-MOS gate arrays. Indirect clustering value is introduced for the blocking, i.e. grouping of modules under block size restriction. The system including the procedure has been successfully applied to the design of MOS gate arrays with effectively no manual assistance.

A "Lookahead" Router for Multilayer Printed Wiring Boards

Abstract: The layout of large multilayer printed wiring boards is a very complex and time-consuming process. The routing portion of the task in particular is difficult because of the number of connections to complete, the number of routing layers which can be used simultaneously and the large size and uniformity of the routing surfaces. The problem is generally well beyond the scope of a designer to grasp as a whole.Automatic techniques for routing are important functions therefore in the multilayer layout process. A good deal of work has been done in the field. [1-5]In this paper we will review a previous technique, describe some of its shortcomings, and present a new and more powerful method which has been successfully employed.

A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem

Abstract: This paper deals with the optimum placement of blocks on a two-dimensional cell-array, which minimizes the total routing length of signal sets. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.

Dynamic Design Rule Checking in an Interactive Printed Circuit Editor

Abstract: This paper describes an interactive system for editing of printed circuit layout designs. Each editing operation is dynamically checked against a set of user-defined design rules to assure that the resulting design is valid.

An Interactive Routing Program with On-Line Clean-Up of Sketched Routes

Abstract: This paper describes a program for interactive layout of printed circuit boards (PCB) with fixed holes. The wires may be drawn as a rough sketch and will be cleaned-up conforming to the specified clearance and wire width. Also included is on-line check of spacing and crossing.

An Application of Branch and Bound Method to Automatic Printed Circuit Board Routing

Abstract: This paper describes an approach to PCB routing which applies the Branch and Bound Method to the search for a path between two points. A special multiple pass method of pseudo-parallel routing is applied in order to insure that simple interconnections are made at the earliest stages. The algorithm has been implemented by Computervision Corporation on a 32K word, 16 bit minicomputer based system.

Placement Algorithm by Partitioning for Optimum Rectangular Placement

Abstract: This paper describes methods for placement of DIP packages on a rectangular grid with minimum crossovers and wire length. The initial step is partitioning the components into subsets, one subset for each row, such that the connection between rows are minimized. An iterative procedure, yielding successively improved partitioning, is used for this purpose. Once the row sets are formed, a process for best placement of the DIP in a row is carried-out. The row is assumed to have either a one row channel for routing wires or two row channels. For both cases a placement which minimized crossovers and line length is obtained. The basic method uses simple branch and bound search procedures for placing the packages within a row set. In the placement procedure the objects being placed are wire nets rather than components. Previous work related to this problem is included in references [1-6].

Use of Floyd's Algorithm to Find Shortest Restricted Paths.

Abstract: In a directed network with no negative circuit, Floyd's algorithm finds, for each pair of nodes x and y, a shortest path from x to y. Here the procedure is extended to minimize more general length-functions over sets of paths that are restricted in various ways.

A Methodology for Optimal Design of Water Distribution Systems.

Abstract: : A comprehensive methodology for the design of municipal water distribution systems that explicitly incorporates reliability and performance into the system design is developed The complex design problem is decomposed within the context of a three-level hierarchically integrated system of models The first and second level models combine to select the links in the distribution system layout The third level model accomplishes the detailed system design for the layout from the upper level models Two alternative first level models, a shortest path tree and a nonlinear programming model, are developed to select the minimum cost tree layout Two second level, complementary 0-1 integer programming models are developed to select the loop-forming links for the minimum cost tree layout The third level nonlinear programming model optimizes the detailed distribution system design (link diameters, pump capacities, elevated storage heights, and valve resistance) of the resulting network layout with respect to distribution system performance under expected emergency loading conditions (fire demand, broken links, pump outage) This detailed design is performed subject to satisfying steady state conditions, minimum performance levels under normal loading conditions, and maximum budget level The methodology is applied to the design of a real life water distribution system (Author)

Automatic Pipe Routing and Material Take-Off System for Chemical Plant

Abstract: An automatic pipe routing system for chemical plants is described. This system determines routes of pipes and positions of fittings and summarizes piping material data.

Keyboard verification system and method

Abstract: Keyboard key movement is verified with a high degree o accuracy in a manner largely immune to ambient noise or other electronic or electromagnetic interference. A pulse signal in the form of a train of pulses, is periodically applied to the circuit associated with each key. The signal coupled through the key-controlled circuit is reconstructed only if it exceeds a predetermined reference level. A test, which depends on the previously verified key state, is made to determine the existing key state. The test for the active key state is conditioned on multiple true comparisons of a reconstructed signal with the originally applied signal throughout the duration of the test. The test for the inactive key state is conditioned on the absence of a reconstructed signal throughout the test. In both instances the newly indicated key state is compared with the state to which the key is assumed to have changed from its previsouly verified state. If the test fails, the key is considered to have remained in its previously verified state. Immunity to noise is enhanced by making the pulse signal a pseudo-random signal which is successively applied across the key-controlled circuits in a timing sequence out of synchronism with the generation of the pulse signal. The system disclosed avoids the requirements for massive shielding, for selective routing of conductors, or for the assignment of special, physical key locations in the electronic scanning sequence, while providing fully verified key actuation at reduced overall system cost.