Showing papers on "Routing (electronic design automation) published in 1980"

Method for traffic determination in a routing and information system for individual motor vehicle traffic

Abstract: In a method for traffic determination, a routing and information system for individual motor vehicle traffic is used, in which by way of stationary routing station poles, route information and local information are transmitted to the passing vehicles. For the determination of the traffic situation, the traveling times between two routing station poles are measured in individual vehicles with timing units. These traveling times are transmitted, together with the local information of the first routing station pole passed by a vehicle, to the second routing station pole and are considered in determining new route recommendations.

Modelling of rail networks: Toward a routing/makeup model

Abstract: Freight flow management in rail systems involves multicommodity flows on a network complicated by node activities (queueing and classification of cars at marshalling yards). Routing in these systems should account for technology requirements of motive power and traction as well as resource allocation (cars to blocks, blocks to trains). In this paper, we propose a hierarchial taxonomy of modelling issues and describe a class of models dealing with car routing and train makeup from the viewpoint of network flows and combinatorial optimization. We compare our model with two previous rail network models and discuss possibilities for algorithmic development.

Queuing Network Models with State-Dependent Routing

Abstract: A model of a closed queuing network within which customer routing between queues may depend on the state of the network is presented. The routing functions allowed may be rational functions of the queue lengths of various downstream queues which reside within special subnetworks called p-subnetworks. If a network with no state-dependent routing has a product-form joint equilibrium distribution of the queue lengths, then the introduction of these routing functions will preserve the product form of the equilibrium distribution. An example to illustrate the applicability of the model to the problem of analyzing a load balancing strategy is presented. It is also indicated how the parametric analysis of a network with routing functions can be simplified through the analysis of a simpler “equivalent” network.

Algorithms for integrated circuit layout: an analytic approach

Abstract: In this thesis, the problem of designing the layout of integrated circuits is examined. The layout of an integrated circuit specifies the position of the chip of functional components and wires interconnecting the components. We use a general model under which components are represented by rectangles, and wires are represented by lines. This model can be applied to circuit components defined at any level of complexity, from a transistor to a programmable logic array (PLA). We focus on the standard decomposition of the layout problem into a placement problem and a routing problem. We examine problems encountered in layout design from the point of view of complexity theory. The general layout problem under our model is shown to be NP-complete. In addition, two problems encountered in a restricted version of the routing problem --channel routing--are shown to be NP-complete. The analysis of heuristic algorithms for NP-complete problems is discussed, and the analysis of one common algorithm is presented. The major result presented in this dissertation is a polynomial time algorithm for a restricted case of the routing problem. Given one rectangular component with terminals on its boundary, and pairs of terminals to be connected, the algorithm will find a two-layer channel routing which minimizes the area of a rectangle circumscribing the component and the wire paths. Each terminal can appear in only one pair of terminals to be connected, and the rectangle used to determine the area must have its boundaries parallel to those of the component. If any of the conditions of the problem are removed, the algorithm is no longer guaranteed to find the optimal solution.

Complexity Theory and Design Automation

Abstract: Complexity Theory is discussed and its relationship to Physical Design (i.e. Placement/Wiring) and Test Pattern Generation is shown and developed.

Kinematic wave routing incorporating shock fitting

Abstract: An analytical solution to the kinematic wave approximation for unsteady flow routing is presented. The model allows time-dependent lateral inflow with piecewise spatial uniformity and can be applied to complex kinematic cascades. Kinematic shocks are considered as manifestations of higher-order effects such as rnonoclinal flood waves, bores, etc. Within the context of kinematic approximation therefore we retain their dynamic effects by routing the discontinuities as they appear. Certain simplifying assumptions are made which permit closed form solutions and an efficient numerical algorithm, based on the method of characteristics, is employed. The resulting model, called an approximate shock-fitting scheme, preserves the effect of the shocks without the usual computational complications and compares favorably with an implicit finite difference solution. The efficiency and accuracy of the new method are illustrated by computing a variety of unsteady flows, ranging from simple cascades to complex natural watersheds.

A Line-Expansion Algorithm for the General Routing Problem with a Guaranteed Solution

Abstract: A new routing algorithm is presented which is based on the expansion of a line in the direction perpendicular to the line The line-expansion principle is first applied to the single layer routing problem For the routing on two layers only some minor modifications have to be made An important extension is added in which the search for an interconnection from a given point is initiated in more than one direction at the same time The major advantage of the line-expansion algorithm over the well-known line-search algorithm is the guarantee that always a solution will be found if one exists

An algorithm for single-row routing with prescribed street congestions

Abstract: The single-row routing approach for layout has attracted a great deal of interest and is in a position to become one of the fundamental routing methods for high density multilayer printed wiring boards (PWB's). A specific development has recently been accomplished on this approach [12], namely: Necessary and sufficient conditions for optimum routing have been obtained. Nonetheless, there still remains a fundamental problem to be overcome, that is, to develop an algorithm to find the optimum solution. The present paper derives an alternate set of necessary and sufficient conditions for the same problem. These are easy to check and are tailored for algorithm development. An efficient algorithm in the special cases of upper and lower street congestions up to two has been proposed. These special cases are particularly of interest in the design of practical PWB's.

A polynomial time algorithm for optimal routing around a rectangle

Abstract: In this paper we present an algorithm for a special case of wire routing. Given a rectangular circuit component on a planar surface with terminals around its boundary, the algorithm finds an optimal set of paths in the plane connecting specified pairs of terminals. The paths are restricted to lie on the outside of the component and must consist of line segments orthogonal to the sides of the component. Paths may intersect at a point but may not overlap. The criterion for optimality is the area of a rectangle with sides orthogonal to those of the component which circumscribes the component and paths. The algorithm has running time O(t3), where t is the number of terminals on the component.

A class of optimal routing algorithms for communication networks

Abstract: : This report describes an algorithm for minimum delay routing in a communication network. During the algorithm each node maintains a list of paths along which it sends traffic to each destination together with a list of the fractions of total traffic that are sent along these paths. At each iteration a minimum marginal delay path to each destination is computed and added to the current list if not already there. Simultaneously the corresponding fractions are updated in a way that reduces average delay per message. The algorithm is capable of employing second derivatives of link delay functions thereby providing automatic scaling with respect to traffic input level. It can be implemented in both a distributed and a centralized manner, and it can be shown to converge to an optimal routing at a linear rate.

An Over-The-Cell Router

Abstract: A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.

Comparison of Muskingum Method Difference Schemes

Abstract: This note will center on the issue of numerical precision as affected by the use of different routing schemes. The investigation is prompted by the observation that in an application of the Kalinin-Miljukov method, accuracy improved when a more refined difference scheme was used in place of the conventional one.

Efficient Placement and Routing Techniques for Master Slice LSI

Abstract: This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.

Guidelines for applying criteria to designate routes for transporting hazardous materials. implementation package

Abstract: Techniques are explained that may be used for evaluating alternative highway routes for hazardous materials movements. The criteria that may be applied for hazardous materials routing is briefly described and their application is illustrated by an example. Current routing practices, with existing regulatory requirements, are described as background. An overview of the routing method is followed by a description of the guidelines and procedures for applying the routing criteria. The concept of risk is defined and each step in the route selection explained. A hypothetical case study illustrates the application of the routing procedures; the example includes personal and property risk calculations and illustrates the techniques for analyzing urban arterials and rural highways. Blank worksheets and forms for structuring and conducting the routing analyses are appended.

A note on determining operating strategies for probabilistic vehicle routing

Abstract: The stochastic vehicle routing problem is a problem of current importance and research interest. Applications include schoolbus routing, municipal waste collection, subscription bus scheduling, daily delivery of dairy goods, and a host of related transportation and distribution activities. In this paper, we assume that routes for vehicles have already been generated and we focus on determining operating strategies. That is, under what conditions should a driver return to the central depot in order to replenish his supply? We present a dynamic programming recursion which addresses this question and we show that the optimal policy is of a rather simple form. Finally, an algorithm and example illustrate the policy.

Restructurable VLSI Program

Abstract: : The objective of the Restructurable Very Large Scale Integration (RVLSI) Program is to develop and demonstrate techniques which will make possible integration of large systems as single-package modules. We are developing techniques for restructuring large-area IC chips after fabrication in order to provide access for testing, perform defect avoidance and customization, and reconfigure a system while it is being used. The DARPA-sponsored program is focused on development or architectural concepts for data- and signal-processing systems for RVLSI implementation, development of design aids for unique RVLSI design problems, and development of test techniques suitable for RVLSI applications. An overview of the goals and proposed techniques is given in Sec. II. In Sec. III the functional requirements on programmable connections or links are presented and three types of links are described and compared. In the near term the emphasis will be on laser programmed links and links made from standard logic circuitry; a longer-term goal is development of an electrically programmable nonvolatile link. In Sec. IV we describe a hardware description language designed for efficient description of hierarchical and iterative structures of digital circuits. Since each RVLSI chip may have a different wiring configuration, complete automation of the signal routing process is essential. Solutions for this problem are presented in Sec. IV. Results of an investigation of mapping a regular locally connected array of processing elements onto a physical array with defective elements are presented in Sec. V. An integrator for a spread-spectrum packet radio receiver has been chosen for a first implementation.

Automated Optical Inspection Of Multilayer Printed Circuit Boards

Abstract: The Inspectron is an instrument which will perform an automatic optical inspection of the etched circuitry on the individual layers of a multilayer printed circuit board.The concept of this instrument is unique in that it does not compare the PCB under test with a master or with computer-stored data. Instead, as the board is optically scanned, a small area is re-imaged onto a detector array. The detector signals, after digitization, are fed into high-speed logic circuitry which is programmed to distinguish between the ap­ pearance of a good board and an error. An 8 x 10 inch board can be inspected for line width, line spacing, line breaks, excess copper, and voids in about a minute. The Inspectron can also inspect pads for completeness and ground planes for shorts.IntroductionA typical modern printed circuit board manufacturing facility is an interesting study in contrasts. Most of the fabrication operations - printing, plating, drilling, routing - are heavily automated. But, in the Inspection Department, there are often dozens of inspectors with magnifiers visually checking the boards and artwork for flaws. It turns out that in many cases, the inspection of a PCB is as expensive as its manufacture.About four years ago, Advanced Controls began to investigate the possibility of automat­ ing this labor-intensive activity. From the beginning, it was decided to concentrate our efforts on the inner layers of multilayer PCBs for the following reasons:1. They are reported to be the most difficult to inspect because of the small line widths and the density and complexity of the patterns.2. One hundred percent visual inspection of inner layers is usually mandatory due to the expense of rejecting a complete, laminated board at final electrical test.3. Most multilayer boards today are computer designed and plotter generated, which im­ plies a uniformity of lines and spaces as well as an absence of lettering and other extra­ neous markings in the circuitry areas.Comparison MethodsInitially, our investigation centered around the concept of an image comparison technique using either a master PCB, the artwork, or a computer-stored map. However, the more deeply this concept was pursued, the more troublesome were the problems encountered. For instance, since the instantaneous area of the scanned image, or pixel-under-test, must match the cor­ responding area of the master, exact alignment, In two axes and an angle, would be necessary at every point on the board. Shrinking or expanding of the board due to changes in tempera­ ture or humidity would have to be compensated for, as would the normal and perfectly accept­ able variations in the widths of the lines and spaces of the pattern. It soon became rather evident that the complexities introduced to solve these problems would probably make the resulting instrument only marginally economical as a replacement for human Inspectors.The same problem occurs when a comparison of the optical Fourier transform is made. In this case, if a line at the edge of a scanned area was included in one field of view and omitted from the other as a result of misalignment, the Fourier energy distributions would not match.Characteristic MethodOn the other hand, a human inspector seldom makes use of a direct comparison with a master; instead, she scans the board under test to insure that every point on it has the general characteristics of a good PCB. These characteristics were tabulated and found to be:1. All circuit lines end in pads. Any line that does not is almost certainly broken, and can be considered an error.

A Neighbor Connected Processor Network for Performing Relational Algebra Operations

Abstract: In a data base computer consisting of cells with processing capability, the desired goal is to achieve an execution time - for each data base operation - to be inversely proportional to the number of cells. Using rings as a basic building block, we have constructed different intercell communication networks. The capacity of the communication network have been analyzed under the workload of relational algebra operations. A k-dimensional network of intersecting rings, each of 2 or 3 cells have been found to give the highest processing capacity per cell in the network. Here k is log2C, where C is the total number of cells.A simple wiring scheme for k-dimensional network of 2 cells per ring has been presented. For this type of network, we have also described the routing logic, and given an estimate of the queueing delay.

The Standard Transistor Array (STAR) Part II Automatic Cell Placement Techniques

Abstract: Layout of a STAR device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. Cell placement must be such that routing is not hindered. Also, placement procedures must be cost effective and easy to implement on a digital computer. A placement procedure for STARs is described in this paper that satisfies these characteristics. The procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing VIA requirements. Computer implementations of the procedure are discussed. Experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.

Center-based broadcasting

Abstract: We consider the problem of routing broadcast messages in a loosely-coupled store-and-forward network like the ARPANET. Dalal discussed a solution to this problem that minimizes the cost of a broadcast; in contrast, we are interested in performing broadcast with small delay. Existing algorithms can minimize the delay but seem unsuitable for use in a distributed environment because they involve a high degree of overhead in the form of redundant messages or data-structure space. We propose the schemes of center-based forwarding; the routing of all broadcasts via the shortest-path tree for some selected node called the center. These algorithms have small delay and also are easy to implement in a distributed system. To evaluate center-based forwarding, we define four measures of the delay associated with a given broadcast mechanism, and then propose three ways of selecting a center node. For each of the three forms of center-based forwarding we compare the delay to the minimum delay for any broadcasting scheme and also to the minimum delay for any single tree. In most cases, a given measure of the delay on the centered tree is bounded by a small constant factor relative to either of these two minimum delays. When it is possible, we give a tight bound on the ratio between the center-based delay and the minimum delay; otherwise we demonstrate that no bound is possible. These results give corollary bounds on how bad the three centered trees can be with respect to each other; most of these bounds are immediately tight, and the rest are replaced by better bounds that are also shown to be tight.

Mail sorting apparatus and system

Abstract: A system for routing correspondence from a first location including a plurality of slot entries to a predetermined conveyor path to a second, discharge location. A collection assembly is disposed at the discharge location for collection of routed correspondence along two adjacent conveyor paths.

Some Results Concerning Data Routing in Array Processors

Abstract: Some properties of k-dimensional cyclic networks are derived and used to give some algorithmic timings for the transposition of rectangular sets of data in an array processor's memory. General results are produced which can be applied to ICL's distributed array processor (DAP).

On B-trees: routing schemes and concurrency

Abstract: In recent years B-trees have become a common data structure for representing large data dictionaries. In this paper we investigate the often ignored relationship between routing schemes and the permissible operations in leaf-search B-trees. We show that among the many commonly used routing schemes in the literature, some are cleaner than others, making them more attractive for leaf-search B-trees supporting concurrency.

Cell Map Representation for Hierarchical Layout

Abstract: In the hierarchical layout of rectangular blocks, the routing area naturally breaks into a set of adjacent rectangles. These rectangles can be used as a basis for both loose routing and the final track assignment. The paper explores some ways of structuring the required data. More details about generalized Lee routing, and practical results are left for verbal presentation.

Universal timing array

Abstract: A universal timing array (UTA) comprising a branch and increment logic circuit and multiple 2-bit counter cells is fabricated as a single large scale integrated circuit and is adapted to implementing various timing and control functions in digital computers and radar signal processors. Implementation of the UTA functional design using emitter coupled logic circuitry and special circuit design features improves UTA performance by increasing operating clock frequency, widening operating temperature range and reducing on-chip complexity. A specific embodiment utilizes a standard universal digital array chip having specially selected cell placements and interconnecting routing patterns.

ARPANET Routing Algorithm Improvements. Volume 1

Abstract: : This report covers work performed during the first year of the extension of the ARPANET Routing Algorithm Improvements Contract. Network buffer management issues are discussed and a new buffer management scheme for the ARPANET is designed. Logical addressing is discussed, and a design is given for a logical addressing scheme suitable for ARPANET or DIN II. The applicability of ARPANET Routing to DIN II is evaluated. The possibility of extending ARPANET's routing algorithm to provide multiple routes between a given pair of nodes is discussed, and a preliminary design is proposed, which, however, still contains a number of unsolved problems. A set of metrics for evaluating congestion control algorithms is proposed, and AUTODIN II congestion control scheme is evaluated. A new congestion control scheme, suitable for networks containing ARPANET routing, is proposed. BBN's network simulator is described, and its command language is specified. Various simulation design decisions are discussed. The statistical properties of simulation data are discussed and various techniques for analyzing and interpreting simulation data are proposed.