Showing papers on "Routing (electronic design automation) published in 1981"

A generalized assignment heuristic for vehicle routing

Abstract: : We consider a common variant of the vehicle routing problem in which a vehicle fleet delivers products stored at a central depot to satisfy customer orders. Each vehicle has a fixed capacity, and each order uses a fixed portion of vehicle capacity. The routing decision involves determining which of the demands will be satisfied by each vehicle and what route each vehicle will follow in servicing its assigned demand in order to minimize total delivery cost. We present a heuristic for this problem in which an assignment of customers to vehicles is obtained by solving a generalized assignment problem with an objective function that approximates delivery cost. This heuristic has many attractive features. It has outperformed the best existing heuristics on a sample of standard test problems. It will always find a feasible solution if one exists, something no other existing heuristic can guarantee. It can be easily adapted to accommodate many additional problem complexities. By parametrically varying the number of vehicles in the fleet, our method can be used to optimally solve the problem of finding the minimum size fleet that can feasibly service the specified demand.

Capacitated arc routing problems

Abstract: A capacitated node routing problem, known as the vehicle routing or dispatch problem, has been the focus of much research attention On the other hand, capacitated arc routing problems have been comparatively neglected Both classes of problems are extremely rich in theory and applications Our intent in this paper is to define a capacitated arc routing problem, to provide mathematical programming formulations, to perform a computational complexity analysis, and to present an approximate solution strategy for this class of problems In addition, we identify several related routing problems and develop tight lower bounds on the optimal solution

State‐space relaxation procedures for the computation of bounds to routing problems

Abstract: It is well-known that few combinatorial optimization problems can be solved effectively by dynamic programming alone, since the number of vertices of the state space graph is enormous. What we are proposing here is a general relaxation procedure whereby the state-space associated with a given dynamic programming recursion is relaxed in such a way that the solution to the relaxed recursion provides a bound which could be embedded in general branch and bound schemes for the solution of the problem. This state space relaxation method is analogous to Langrangian relaxation in integer programming. This paper gives a survey of this new methodology, and gives, as examples, applications to the traveling salesman problem (TSP), the timeconstrained TSP and the vehicle routing problem (VRP). Valid state space relaxations are discussed for these problems and several bounds are derived in each case. Subgradient optimization and “state space ascent” are discussed as methods of maximizing the resulting lower bounds. More details of the procedures surveyed in this paper can be found in [2 ,3 ,41.

A fast parallel algorithm for routing in permutation networks

Abstract: An algorithm is given for routing in permutation networks-that is, for computing the switch settings that implement a given permutation. The algorithm takes serial time O(n(log N)2) (for one processor with random access to a memory of O(n) words) or parallel time O((log n)3) (for n synchronous processors with conflict-free random access to a common memory of O(n) words). These time bounds may be reduced by a further logarithmic factor when all of the switch sizes are integral powers of two.

Circuit layout

Abstract: This paper gives a general overview of circuit layout, taking a unified approach to various styles of integrated circuits, printed circuit boards, and hybrid circuits. A lot of attention is given to the layout of large and complicated circuits, in particular, to the layout of very-large-scale-integration (VLSI) chips. Though the paper is an overview, and one could almost say a tutorial, it is intended for readers with some basic knowledge of what a circuit layout is and what some of the basic problems are. The main subjects discussed are: assignment of gates, placement methods, loose routing, final routing, and problems associated with the implementation of a hierarchical system. The emphasis is on new, not widely published methods, and on methods that seem to have potential for solving some of the current problems. Practical examples illustrate this rather personal account of circuit layout and sugsest where we may go from here.

Distributed dynamic programming

Abstract: We consider distributed algorithms for solving dynamic programming problems whereby several processors participate simultaneously in the computation while maintaining coordination by information exchange via communication links. A model of asynchronous distributed computation is developed which requires very weak assumptions on the ordering of computations, the timing of information exchange, the amount of local information needed at each computation node, and the initial conditions for the algorithm. The class of problems considered is very broad and includes shortest path problems, and finite and infinite horizon stochastic optimal control problems. When specialized to a shortest path problem the algorithm reduces to the algorithm originally implemented for routing of messages in the ARPANET.

Set partitioning based heuristics for interactive routing

Abstract: The set partitioning model is used as the basis for an interactive approach for solving a broad class of routing problems. A pricing mechanism is developed which can be used with a variety of methods in generating improving solutions. A version of the approach for delivery problems has been implemented via a colorgraphics display. The human aided optimization procedure was tested on the standard 50-point, 75-point, and 100-point test problems of Eilon, Watson-Gandy, and Christofides [6]. In the case of the first two test problems, the procedure was able to generate the best known solutions. In the 100-point problem, a better solution was generated than the current best known solution.

High speed machine for the physical design of very large scale integrated circuits

Abstract: Method and apparatus for the physical design of very large scale integrated (VLSI) circuits, and in particular the interconnection and wire routing between circuits formed on a chip. Apparatus is set forth for determining the wire routings in a VLSI circuit comprised of cells, wherein the cells are composed of electronic devices functioning as logic gates. Groups of cells may be interconnected to function as flip flops, shift registers and the like. A supervisory controller communicates with n, where n is an integer, identical multi-port processors, with one processor dedicated to each cell, for determining the wire routings between the respective cells. Each processor communicates simultaneously with its four adjacent neighbor processors to determine channel routings from one point to the next in the array of cells, wherein a channel routing includes vertical and horizontal paths. Following determination of global channel routings, exact vertical and horizontal tracks for the wire paths are assigned. The array or processors may be utilized to wire a much larger array of cells.

Apparatus using a decision table for routing data among terminals and a host system

Abstract: A router module controls interfaces to (a) terminals, (b) communications to a host system, and (c) a permanent storage device like a digital cassette. The router module utilizes routing logic including a decision table to effect the routing through the interfaces named. The terminals include data entry terminals and a printer module and the router module enables several data entry terminals to utilize the printer module. The router module is located on a substrate which can be mounted in one of the data entry terminals to utilize the associated power supply.

Provably Good Channel Routing Algorithms

Abstract: In this paper we present three new two-layer channel routing algorithms that are provably good in that they never require more than 2d-1 horizontal tracks where d is the channel density, when each net connects just two terminals. To achieve this result, we use a slightly relaxed (but still realistic) wiring model in which wires may run on top of each other for short distances as long as they are on different layers. Two of our algorithms will never use such a “parallel run” of length greater than 2d-1 and our third algorithm will require overlap only at jog points or cross points. Since in this wiring model at least d/2 horizontal tracks are required, these algorithms produce a routing requiring no more than four times the best possible number of horizontal tracks. The second algorithm also has the property that it uses uses at most 4n contacts, where n is the number of nets being connected.

Servicing and real-time control of networks with dynamic routing

Abstract: The design of a network for dynamic routing is made using the forecasted network loads. Load uncertainties arising from errors in the forecast and from daily variations in network load give rise to reserve or idle network capacity not immediately needed by current network demands. The reserve capacity can be reduced by the use of more flexible dynamic routing methods, which allow routing flexibility to help control network flow under load uncertainties. We illustrate techniques for changing network routing patterns in planned and demand servicing to counteract the effects of forecast errors. Included in the benefits are a reduction in both reserve capacity, estimated to be about 5 percent of network first cost, and in trunk rearrangements. We also present call-by-call simulation results for real-time routing enhancements to the basic routing algorithms. The real-time routing algorithms use dynamic trunk reservation techniques, and the simulation results illustrate the improvement in network efficiency and performance under normal daily load variations, network overloads, and network failures.

A Parallel Bit Map Processor Architecture for DA Algorithms

Abstract: Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing architecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability. Also included in this paper are descriptions of algorithms that exploit the architecture. Algorithms for routing, DRC, and bit vector manipulation are included.

An Optimum Layer Assignment for Routing in ICs and PCBs

Abstract: An optimum layer assignment of interconnections in IC and two-layer PCB is derived. The assignment is optimal in the sense that it is achieved through a global minimization of contacts or vias. The problem is formulated as a 0,1 integer program and solved using a branch and bound technique. There are no constraints on contact location or on the number of wires that can be connected at each contact. Applications of this procedure to VLSI circuits are discussed.

The Join-Biased-Queue Rule and Its Application to Routing in Computer Communication Networks

Abstract: A routing rule similar in nature to delta-routing [8] is studied in this paper. The approach is to superimpose, local adaptivity on top of a fixed traffic flow distribution. The fixed flow distribution we choose is obtained from the best stochastic (BS) rule [3]. The adaptive part is called the join-biased-queue (JBQ) rule. The resultant JBQ-BS rule is analyzed on small networks and is shown to provide 10-27 percent delay improvement over the BS rule.

Computation of Power Supply Nets in VLSI Layout

Abstract: For a given placement of macrocells with given power consumption a full automatic layout of power supply and ground nets has been developped. The varying width in different segments of these nets is calculated from local current values resulting in rectangles presenting the net segments. These rectangles are embedded in the routing plane with regard to given design rules.

SHARPS: A Hierarchical Layout System for VLSI

Abstract: A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSI's.

A stochastic model for interconnections in custom integrated circuits

Abstract: A stochastic model for interconnections in integrated circuits composed of unequal size logic blocks separated by routing channels is described. An algorithm, based on the model, is given for estimating channel widths and chip area. The effectiveness of the algorithm is tested through an example. Applications of the model to placement and routing of integrated circuits are discussed.

Optimal Routing in Rectilinear Channels

Abstract: Programs for integrated circuit layout typically have two phases: placement and routing. The router should produce as efficient a layout as possible, but of course the quality of the routing depends heavily on the quality of the placement. On the other hand, the placement procedure would like to know how good a routing it can expect without actually routing the wires. This paper presents fast algorithms for optimal routing and for accurately estimating the area cost of such routings without actually laying them out.

An Automatic/Interactive Layout Planning System for Arbitrarily-Sized Rectangular Building Blocks

Abstract: Layout Planning Aids (LPA) is designed to allow easy generation of topological layout (chip) plans for IC mask designs. The output of LPA is a hard-copy topological plan. The system encourages a hierarchical design style. It encompasses both algorithmic and computer-assisted, designer-controlled approaches to the problem by providing automatic placement and routing facilities plus a set of versatile interactive commands. The interactive features allow designers to work collaboratively with the system such that the strengths of both can be combined to achieve the best results.

A computer assisted school bus routing strategy: A case study

Abstract: The effect of routing changes on the efficiency of suburban-rural pupil transportation systems is demonstrated in a case study of a suburban-rural county in Virginia. A computer assisted routing method was used that included manual route design and computer aided route evaluation. Various policy options affecting routing were identified and new routes were developed. The recommended routes represented a 17% reduction in the number of routes required, a 19% reduction in the number of buses required, and a 57% reduction in the total number of vacant seats. While the computer assisted method used produced a more efficient routing structure, the process of manual route design was still slow and tedious. Techniques such as interactive computer graphics appear to be suited to the school bus routing problem and their use should be explored.

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 2 The Layout Design System Mars-M3

Abstract: Described are the outline and the application results of a fully automatic chip layout design system which has been utilized for years for the development of over a hundred options of ECL and MOS gate arrays. The features and techniques of the placement, routing and checking subsystems as well as the chip layout model which can be treated by the system are discussed.

Modeling and analysis of flow controlled packet switching networks

Abstract: Packet switching networks with flow controlled virtual channels are modeled by closed multi-chain queueing networks. The tree convolution algorithm for an exact analysis of such models is discussed. The algorithm is very efficient when routing chains have sparseness and locality properties that are typical of communication network models. The accuracy of an approximate model of equivalent open chains was investigated. An optimal routing criterion for adding a virtual channel (with a window size of one) to an existing network is explored.

TWIGY A Topological Algorithm Based Routing System

Abstract: A two-level approach to routing is described, in which a multi-layer printed circuit board routing problem is broken down into a set of single-layer ones. A topological transformation is then applied to accomplish single-layer routing. A solution found for each layer by a search in this new domain is then translated back into physical space by means of a deterministic drawing algorithm. The algorithms are independent of specific technological parameters, affording their use on a variety of board routing grids, pad diameters and wire sizes.

Device for locating routing guideways

Abstract: In a device for locating routing guideways of laid lines and cables, a marking element which consists of an LC circuit is assigned to the route. A locator having a transmitting device is used to emit an appropriately tuned frequency which causes resonance behaviour in the LC circuit. The corresponding secondary emissions are picked up by a receiving device and displayed. It is possible in this way to use marking elements of different design in order to discriminate in the case of a plurality of cables or foreign bodies.

The Hughes Automated Layout System - Automated LSI/VLSI Layout Based on Channel Routing

Abstract: The Hughes Automated Layout System (HAL) is intended to provide fast, accurate, and efficient layout of LSI/VLSI circuits. The HAL development plan calls for an evolutionary development in three phases, with each phase providing a usable design system. HAL(I) is limited to standard cell layout and is now operational. HAL(II), which will permit more complex geometries, and HAL(III), which will add hierarchical capabilities, are in initial development. This paper discusses the features of HAL(I), and the concepts of decomposition and ordering of routing domains that underlie the more advanced systems.

A Statistical Model for Net Length Estimation

Abstract: The prerouting estimation of net length is very important to the physical design since the estimated length can be employed as a figure-of-merit of the placement process, as an evaluation of the placement result, and in the calculation of capacitance in the predictive timing analysis. The traditional methods, bounded rectangle method, minimal spanning tree method and minimal Steiner tree method, result in either poor estimation or time consuming processing. Moreover, they do not consider the interference between each net and the technology influence. A statistical model for net length estimation has been developed to overcome these deficiencies. This model provides an unbiased estimate with 7 percent relative root-mean-squares error on an average.