Showing papers on "Routing (electronic design automation) published in 1982"

A "Greedy" Channel Router

Abstract: We present a new, "greedy", channel-router that is quick, simple, and highly effective. It always succeeds, usually using no more than one track more than required by channel density. (It may be forced in rare cases to make a few connections "off the end" of the channel, in order to succeed.) It assumes that all pins and wiring lie on a common grid, and that vertical wires are on one layer, horizontal on another. The greedy router wires up the channel in a left-to-right, column-by-column manner, wiring each column completely before starting the next. Within each column the router tries to maximize the utility of the wiring produced, using simple, "greedy" heuristics. It may place a net on more than one track for a few columns, and "collapse" the net to a single track later on, using a vertical jog. It may also use a jog to move a net to a track closer to its pin in some future column. The router may occasionally add a new track to the channel, to avoid "getting stuck".

Message routing in a computer network

Abstract: An adaptive distributed message routing algorithm that may be implemented in a computer program to control the routing of data messages in a packet message switching digital computer network. Network topology information is exchanged only between neighbor nodes in the form of minimum spanning trees, referred to as exclusionary trees. An exclusionary tree is formed by excluding the neighbor node and its links from the tree. From the set of exclusionary trees received a route table and transmitted exclusionary trees are constructed.

Dynamic behavior of shortest path routing algorithms for communication networks

Abstract: Several proposed routing algorithms for store and forward communication networks, including one currently in operation in the ARPANET route messages along shortest paths computed by using some set of link lengths. When these lengths depend on current traffic conditions as they must in an adaptive algorithm, dynamic behavior questions such as stability, convergence, and speed of convergence are of interest. This paper is the first attempt to analyze systematically these issues. It is shown that minimum queuing delay path algorithms tend to exhibit violent oscillatory behavior in the absence of a damping mechanism. The oscillations can be damped by means of several types of schemes two of which are analyzed in this paper. In the first scheme a constant bias is added to the queuing delay thereby providing a preference towards paths with a small number of links. In the second scheme the effects of several past routings are averaged as for example when the link lengths are computed and communicated asynchronously throughout the network.

The "PI" (Placement And Interconnect) System

Abstract: "PI" is an advanced LISP-based placement and interconnect system for custom NMOS or CMOS (single-layer metal) designs. When fully implemented, PI will handle placement of arbitrarily-sized rectangular modules, routing of power and ground, signal routing, and compaction. In this paper we briefly review the structure of PI, and present details on the signal-routing heuristics, focusing on the definition of "channels", the global router, the "crossing placer", and the channel routers. The signal router is fully operational; the rest of PI is currently being coded and will be more fully described in later papers and theses.

Spacecraft for Multi-Floor Layout Planning

Abstract: A descriptive problem definition and a tested computerized heuristic solution procedure are offered for the problem of relative location of facilities in or layout of a multi-floor building. The problem definition and solution procedure overcome the problem of severe nonlinearity of inter-department movement times relative to distance, which enter the multi-floor problem because of the indirectness of routing, and because of different movement speeds compared with the single floor case. Both the definition and solution procedure are application-oriented, concentrating on practical aspects of multi-floor space allocation. Substantial savings in an implementation are reported. The procedure is particularly relevant to planning for an organization moving into a new multi-floor building. Additionally, the procedure can be used, without modification, for an organization spread over more than one building, and for single floor facilities. The possibility of alternative inter-floor routings is incorporated.

Routing Schemes for the Augmented Data Manipulator Network in an MIMD System

Abstract: There have been many multistage interconnection networks proposed in the literature for interconnecting the processors that comprise large parallel processing systems. In this paper, the use of the Augmented Data Manipulator and Inverse Augmented Data Manipulator multistage networks in the MIMD mode of operation is considered. A tag based routing scheme which allows distributed control of either network is proposed. Rerouting schemes that allow a message blocked by a busy or known faulty node in its present path to dynamically make use of a nonbusy node and continue, when possible, are described for both networks. Finally, a tag based broadcasting scheme for the networks is introduced that allows one processor to send messages to a subset of the other processors.

On decentralized dynamic routing for congested traffic networks

Abstract: The problem of routing traffic through single destination congested networks is considered, when the network has deterministic inputs and may contain looping paths. A decentralized dynamic routing strategy is proposed which assures that no traffic is directed around loops.

Global Wiring on a Wire Routing Machine

Abstract: A new global wiring algorithm designed for implementation on special purpose physical design machines is described. This algorithm computes more accurate estimates of wiring channel demand and supply than other known algorithms. It also makes better use of this information in determining wire routes. By exploiting the parallel processing capability of an interconnected array of microcomputers, the global wiring is completed effectively and quickly even for large chips.

Automatic layout program for hybrid microcircuits (HYPAR)

Abstract: A computer program for the fully automatic layout of hybrid microcircuits.he program, under certain options, guarantees one-hundred percent routing connectivity for components ranging from discretes to VLSI. Special features such as bottom-up or top-down routing, sequential level routing and user-defined grid spacing provide extensive design flexibility.

On Routing Two-Point Nets Across a Channel

Abstract: Many problems that arise in general channel routing manifest themselves in simpler situations. We consider connecting a set of n terminals on a line to another set on a parallel line across a rectangular channel. We show that in any solution to the problem that (almost) minimizes the width of the channel (i.e. the distance between the lines the terminals reside on), (i) a net may require as many as O(vn) jogs, (ii) no net routed from top to bottom need ever turn upward in the middle. We also present an efficient algorithm to obtain minimal jogging in river routing, and provide necessary and sufficient conditions for conflict cycle resolution. These and other results are presented in the context of a general survey on routing from a combinatorial complexity point of view.

Automated Rip-Up and Reroute Techniques

Abstract: The ultimate goal of all automated routing systems is to interconnect 100% of the necessary point-to-point electrical connections. However, most automated routing systems fail to find acceptable paths for all required connections because of limited routing resources or problem complexity. Therefore, a cleanup phase is often necessary. During this cleanup phase, connectivity can be improved through a variety of manual and automated techniques. This paper concentrates on one automated technique, rip-up and reroute. Various rip-up and reroute strategies are discussed and evaluated, and experimental results are provided.

Conference routing arrangement

Abstract: A processor controlled conference arrangement is connected to a host switching system. The availability of conference resources (e.g., ports, registers, etc.) and processor real time capacity is measured before a call is forwarded to the conference arrangement.

A New Two-Dimensional Routing Algorithm

Abstract: A new heuristic algorithm for two-dimensional routing utilizing two distinct layers is described. It is assumed that all terminals are on the boundary of a rectilinear routing region with or without cutout sections. Terminals on vertical boundary segments are assumed to be on one layer and those on horizontal boundary segments are on the other layer. This algorithm finds all possible paths with minimum corners for a net and then chooses one of those paths by considering path length, the likelihood of blocking nets not yet routed, the usage of vacant tracks, and the necessity of going through an area expected to be congested. A dynamic data structure is maintained. If h and v are the numbers of horizontal and vertical tracks, n is the number of nets, and t is the number of terminals, then the storage requirement is o(hv) and the time complexity is o((t-n)hv). For h=23, v=64, n=47, and t=130 the storage required is 60K bytes and cpu time is 16 seconds. This algorithm is implemented in the C language on a VAX 11/780 under the Berkeley Unix (FOOTNOTE: Unix is a trademark of Bell Laboratories.) Operating system, as part of the LTX layout system of the layout aids group at Bell Laboratories, Murray Hill.

Thin-film EL panel mounting unit

Abstract: A mounting unit for a thin-film EL panel includes a substrate provided with cross-grid electrodes on the back surface thereof having aligned terminals located along the marginal sides thereof and a printed circuit board provided with a plurality of conductive paths on the front surface thereof having aligned end portions located along the side portions thereof. The printed circuit board is provided with plated-through connecting holes and routing holes. Some of the conductive paths on the front surface of the printed circuit board are connected to some of the connecting holes and others of the conductive paths are connected to the routing holes. The back surface of the printed circuit board is provided with conductive paths connecting the routing holes to others of the connecting holes. Plug connectors for electrical circuit means are positioned on the back of the printed circuit board with their leads respectively connected to the connecting holes. The printed circuit board and the substrate are held together with strips of conductive elastomeric connectors sandwiched between the aligned end portions of the conductive paths on the front surface of the printed circuit board and the aligned terminals of the electrodes on the back surface of the substrate.

Double‐row planar routing and permutation layout

Abstract: Problems on layout for ICs (integrated circuits) and PCBs (printed circuit boards) are usually solved by heuristic approaches because they are complex. This article considers a special problem of double-row planar routing. The problem represents a generalization of the permutation layout problem to which estimation of bounds and some algorithms have been proposed recently. Our approach is based on the interval graphical representation introduced in the single-row single-layer PCB problem. The objective function for minimization is the breadth of the realization, i.e., the total number of vertical tracks required to realize a given net list specified in terms of terminals on two parallel rows. The problem is shown to be intractable in the sense of NPcompleteness; however, a polynomial-time heuristic algorithm is proposed. An upper bound for the breadth for an initial solution is given. Iterative improvement is next used. The algorithm has been programmed in FORTRAN and ran on the VAX 11/780 computer.

Three layers are enough

Abstract: In this paper we show that any channel routing problem of density d involving two-terminal nets can always be solved in the knock-knee mode in a channel of width equal the density d with three conducting layers. An algorithm is described which produces a layout of n nets with the following properties: (i) it has minimal width d; (ii) it can be realized with three layers; (iii) it has at most 3n vias; (iv) any two wires share at most four grid points.

On Routing for Custom Integrated Circuits

Abstract: This paper presents a novel and effective strategy for routing custom integrated circuits as well as solutions to subproblems associated with this strategy. Given an initial placement of rectangular blocks, the routing strategy includes the following major steps: construction of a channel graph, estimation of channel widths (based on a statistical model for signal nets and topological routing of power and ground nets), placement modification to include the estimated channel widths, topological routing for signal nets, and finally track assignment. Besides presenting an overview of our strategy, the following topics will be discussed in some detail: (1) necessary and sufficient conditions and a simple algorithm for single layer topological routing of power and ground nets, (2) a quadratic programming formulation for the placement modification problem, and (3) a fast algorithm for obtaining topological routes for signal nets.

Software Communication Mechanisms: Procedure Calls versus Messages

Abstract: Procedure calls and messages are two software communication techniques in wide use today. Whereas the semantics of the procedure call are well-known, the newness and variety of message communication make it less understood. Furthermore, the terms \"procedure calls\" and \"messages\" are often used in a general and imprecise manner, and therefore the differences between them tend to blur. This happens, for example, when the claim is made that messages can be programmed using procedure calls-a claim that is both true and, in fact, reflects what is often done in practice. However, this line of reasoning suggests that there is no difference between procedure calls and messages, simply because both can be programmed with a Turing Machine. This is not the point. If precise syntax and semantics are attributed to both procedure calls and messages, then a reasonable comparison can be made and significant differences between these software communications mechanisms do arise. In other words, if both procedure calls and messages are available, how does a user perceive their differences and similarities? The syntax and semantics of the procedure call are a function of the language being used. In this article, the precise semantics of the PL/I procedure call are used because PL/I is typical of many other languages, such as Algol, Fortran, and Ada. Also, in PL/I additional variations of the procedure call are available (coroutines, tasks, and interrupts), and discussions of these contribute to the understanding of the comparison between procedure calls and messages. Choosing precise syntax and semantics for message communication is a more difficult task than it is for a procedure call because there are no standards for messages and the terminology of the subject is not as widely known.

Hierarchical Top-Down Layout Design Method for VLSI Chip

Abstract: A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.

An Efficient Variable-Cost Maze Router

Abstract: A variable cost maze router is described. The router is substantially faster than most other maze routers and also provides a flexibility which is valuable in a variety of ways. It is particularly well suited for use on multiple layer routing surfaces in which adjacent layers have primary wire directions which are perpendicular to each other. The router has been incorporated as a final phase into both a circuit board routing system and an LSI gate array router. Experience with these systems is described. Potential applications of the variable cost ability are also discussed.

Three layers are enough

Abstract: In this paper we show that any channel routing problem of density d involving two-terminal nets can always be solved in the knock-knee mode in a channel of width equal the density d with three conducting layers. An algorithm is described which produces a layout of n nets with the following properties: (i) it has minimal width d; (ii) it can be realized with three layers; (iii) it has at most 3n vias; (iv) any two wires share at most four grid points.

A Bus Router for IC Layout

Abstract: This paper describes a bus router that is part of a custom IC mask layout system called CIPAR. CIPAR works with rectangular building blocks of arbitrary dimensions. The router is designed specifically to handle power and ground buses. It can route these nets completely on one metal layer. The router also automatically calculates and tapers the bus path width based on current requirements specified in the input circuit description.

Optimal Single Row Router

Abstract: The single row approach represents a systematic suboptimal approach to the general multilayer rectilinear wire routing problem. With this approach, the single row wiring problem (i.e., one where all the points are collinear) forms the backbone of the general multilayer wiring problem. We consider the problem of generating minimum width layouts for single row wiring problems. Our algorithm, which is not grid-based, is enumerative and uses a strong bounding criterion.

Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing

Abstract: The architecture of the Cytocomputer?, an existing special-purpose, pipelined cellular image processor, is described. A formalism used to express cellular operations on images is then given. Cellular image processing algorithms are then developed that perform (1) design rule checks (DRC's) on VLSI circuit layouts, and (2) Lee-type wire routing. Two sets of cellular image processing transformations for checking the Mead and Conway design rules and for Lee-routing have been defined and used to program the Cytocomputer. Some experimental results are shown for these cellular implementations.

Apparatus for automated less-than-truck load shipments

Abstract: A knock-down support system for standard-sized containers which enables the containers to be automatically handled on rails, hangers or the like for routing, loading and unloading onto trucks.

Control techniques and performance models for circuit switched networks

Abstract: A unified control-theoretic model is presented for routing and network management techniques is circuit switched networks. Various traditional and recently proposed schemes are illustrated in terms of this common framework. Properties of the function relating performance to control variables are derived and the issue of user versus system optimization is discussed. Approximate performance models are compared with an exact Markov chain analysis in the context of small networks employing a range of two link alternate routing policies. The exact performances are obtained through a numerical solution to the balance equations in the state probabilities, a procedure which is only feasible for small networks. The most favourable approximate models have been implemented which enable the numerical performance evaluation of the large asymmetric networks found in practice. Performance results for various routing schemes are then obtained using this model for typical networks with non-uniform traffic loads. An analytic solution to the approximate model has been obtained in the case of symmetrical networks with uniform traffic. This model has been found useful in the interpretation of numerical results.