Showing papers on "Routing (electronic design automation) published in 1983"

Hierarchical Wire Routing

Abstract: We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.

Global Wiring by Simulated Annealing

Abstract: Simulated annealing, a new general-purpose method of multivariate optimization, is applied to global wire routing for both idealized (synthetic) and actual designs of realistic size and complexity. Since the simulated annealing results are better than those obtained by conventional methods we use them as a standard against which to compare several sequential or greedy strategies commonly employed in automatic wiring programs.

Iterative method for establishing connections and resulting product

Abstract: A method for establishing connections by automatically routing a plurality of paths between individual components using initially simple connection path shapes. The method is used to create an interconnection package with better use of wiring space. Each connection, in turn, is removed if previously routed, rerouted and evaluated according to specified penalty costs to minimize undesirable routing characteristics. This method is particularly advantageous in providing automatic path routing in directionally uncommitted planes for wiring highly integrated electric circuits, or the like.

Fault-Tolerant Broadcast of Routing Information.

Abstract: An algorithm is presented for the reliable broadcast of routing information throughout a network. The algorithm anticipates the possibility of long-delayed packets, line and node outages, network partitions, hardware failures, and a history of arbitrarily corrupted databases throughout the network. After any failure, the algorithm stabilizes in reasonable time without human intervention, once any malfunctioning equipment is repaired or disconnected. The algorithm also has the advantages of not requiring frequent control traffic in the absence of topological changes, not imposing artificial delays on nodes upon startup, and not relying on timers in ordinary operation. The algorithm is compared to a functionally similar algorithm in the ARPANET.

A Minimal Technology Routing System for Meals on Wheels

Abstract: A novel routing system based on a new travelling salesman heuristic was successfully implemented to handle the efficient daily routing of a varying number of vehicles to more than 200 delivery points whose locations change daily. The system had to be easily mantained by one person and require no resources for example, no computer. Our system achieved these objectives, cost less than $50, and, moreover, shortened average travel times by 13% compared to previous performance.

Hierarchical Channel Router

Abstract: The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 x n) grid and on consistent utilization of a "divide and conquer" approach. For the current implementation of the algorithm, the running time is proportional to N x n x log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's "difficult example" - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.

A graph-theoretic via minimization algorithm for two-layer printed circuit boards

Abstract: Based on graph theory, an efficient via minimization algorithm for certain types of two-layer printed circuit boards is developed which can be executed in polynomial time. The algorithm yields solutions for routings with junctions of degrees varying from 2 to 8 and guarantees the minimum number of vias for routings with three or fewer line segments connected to each junction. Examples are given to illustrate various aspects of the algorithm. In addition, preassignment of line segments on a particular layer of the board due to certain prescribed board (or component) constraints is discussed.

A tree convolution algorithm for the solution of queueing networks

Abstract: A new algorithm called the tree convolution algorithm, for the computation of normalization constants and performance measures of product-form queueing networks, is presented. Compared to existing algorithms, the algorithm is very efficient in the solution of networks with many service centers and many sparse routing chains. (A network is said to have sparse routing chains if the chains visit, on the average, only a small fraction of all centers in the network.) In such a network, substantial time and space savings can be achieved by exploiting the network's routing information. The time and space reductions are made possible by two features of the algorithm: (1) the sequence of array convolutions to compute a normalization constant is determined according to the traversal of a tree; (2) the convolutions are performed between arrays that are smaller than arrays used by existing algorithms. The routing information of a given network is used to configure the tree to reduce the algorithm's time and space requirements; some effective heuristics for optimization are described. An exact solution of a communication network model with 64 queues and 32 routing chains is illustrated.

Routing Techniques for Gate Array

Abstract: This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters. A routing model and hierarchical decomposition schemes are presented to address the routability issue. More specifically, this paper focuses on the formulation and analysis of global routing and vertical assignment problems and gives a systematic breakdown of the routing task into well-defined subtasks. Instead of performing sequential routing, techniques and formulations are introduced to achieve a high degree of order independency in all subtasks. In routing subtasks where iterations are required, independent selection and interconnection are performed to avoid order dependency in typical routing problems. Implementation results are provided to indicate the efficiency of the system.

Optimal Placement for River Routing

Abstract: River routing is the problem of connecting a set of terminals a 1,…,a n on a line to another set b 1,…,b n in order across a rectangular channel. When the terminals are located on modules, the modules must be placed relative to one another before routing. This placement problem arises frequently in design systems like bristle-blocks where stretch lines through a module can effectively break it into several chunks, each of which must be placed separately. This paper gives concise necessary and sufficient conditions for wirability which are applied to reduce the optimal placement problem to the graph-theoretic single-source-longest-paths problem. By exploiting the special structure of graphs that arise from the placement problem for rectilinear wiring, an optimal solution may be determined in linear time.

The DARPA Internet: Interconnecting Heterogeneous Computer Networks with Gateways

Abstract: Armies of spiders could not weave a wider web networks are everywhere. Networks span continents and oceans; tie office buildings in iiles of wire, fiber, and other nerse media; reach into land, air, and space vehicles; and confront microcomputers as well as large maint'rame computers. Someii networks are incredibly fast and others are pragmatically slow; some work better than others, and some do not work well at all. However, despite the present abundance, new networks are still being developed coinstantly to challeinge the competitioni. If' we had a way to initerconnect various networks, many problems could be solved. For example, a user may want to comiimuilicate with a site that is not on the same public network as the host computer. Perhaps there are sev eral hosts but no single network to which they will all coinnect. In some cases, the cost of coninection will be a factor; coninecting 100 hosts on a coaxial local net is more cost-effective than putting them all on a public net, but running 1000 miles of coaxial cable to the 101st host is ab.surd. In other cases, pragmatics or the basic laws of nature apply; for example, radio-based networks are about the only choice if mobility is needed. A network technology that supports a maximum of 256 hosts becomies a problenm when you acquire the 257th. G,iven that all hosts caninot be put on a single network, the next best option is to interconniect networks.

An approximation algorithm for manhattan routing

Abstract: @n) tracks. In practice, it appears that the flux never exceeds a small constant. In this case the algorithm performs asymptotically better than the best-known knock-knee algorithm [21], and almost as well as the best-known three-layer algorithm [19], without requiring the use of either knock-knees or three layers of interconnect. In addition, the three-parameter model, which is closer to the design rules of current fabrication technologies, is presented. Under this model, it is shown that every channel can be routed using 2d+O(1) tracks.

The Proof of a Folk Theorem on Queuing Delay with Applications to Routing in Networks

Abstract: It is shown that among all arrival processes (not necessarily stationary or renewal type) for an exponential server queue with specified arrival and service rates, that the arrival process which mmimizes the average delay and related quantities is the process with constant interarrival times. The proof is based on a convexity property of exponential server queues which is of independent interest. The folk theorem provides a lower bound, which is readily computable by existing methods, to the average delay in a network of queues under rather general routing disciplines. A sharper lower bound on average delay is provided for the special case of Generalized Round Robin routing for a Poisson arrival process.

Single Row Routing

Abstract: The automated design of multilayer printed circuit boards is of great importance in the physical design of complex electronic systems. Wire routing is a crucial step in the design process. In this paper, the single row routing problem is considered. First, we discuss the relevance of single row routing in the context of the general routing problem. Then, we show that relaxing the restriction that backward moves are not allowed can result in smaller street congestions when there are at least four tracks in each street. Next, we obtain an O((2k)!kn log k) algorithm to determine whether or not an instance involving n nodes can be laid out (without backward moves) when only k tracks per street are available. With the additional restriction that wires are not permitted to cross streets, an efficient (O(n2)) algorithm is obtained. This restricted problem is shown to be related to a furnace assignment problem.

General River Routing Algorithm

Abstract: A general and practical river routing algorithm is described. It is assumed that there is one layer for routing and terminals are on the boundaries of an arbitrarily shaped rectilinear routing region. All nets are two-terminal nets with pre-assigned (may be different) widths and no crossover between nets is allowed. The minimum separation between the edges of two adjacent wires is input as the design rule. This algorithm assumes no grid on the plane and will always generate a solution if a solution exists. The number of corners is reduced by flipping of corners. An analysis to determine the minimum space required for a strait-type river routing problem is included. Let B be the number of boundary segments and T be the total number of terminals. The time complexity is of O(T(B+T) /sup 2/) and the storage required is O((B+T) /sup 2/). This algorithm is implemented as part of the design station under development at the University of California, Berkeley.

Global wire routing in two-dimensional arrays

Abstract: We examine the problem of routing wires on a VLSI chip, where the pins to be connected are arranged in a regular rectangular array. We obtain tight bounds for the worst-case "channel-width" needed to route an n × n array, and develop provably good heuristics for the general case. An interesting "rounding algorithm" for obtaining integral approximations to solutions of linear equations is used to show the near-optimality of single-turn routings in the worst-case.

Improved Compaction by Minimized Length of Wires

Abstract: The compaction of IC or hybrid layouts by means of the "longest path" method yields a slack in the placement of part of the elements, which, in its turn, can be used to reduce the overall wire-length. The result is an improved electrical performance and a smaller layout. The optimization problem was transformed to a graph-theoretical problem in a way similar to the compaction problem itself. Our procedure starts by adding pieces of information out of the connectivity of the layout to the constraint graph. The succeeding heuristic algorithms generate a new tree of longest paths, taking the linear inequalities and the result of the longest path calculation into consideration. A few examples demonstrate the significant reduction of wire-length and sometimes even an additional reduction of layout area achieved with low computational effort.

An Automatic Routing Scheme for General Cell LSI

Abstract: An automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown.

An Over-Cell Gate Array Channel Router

Abstract: A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. Macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. Each loose horizontal channel segment is assigned to a channel track using a maze router. Vertical channel segments are completed by a modified dogleg channel router.

DCN local-network protocols

Abstract: This RFC provides a description of the DCN protocols for maintaining connectivity, routing, and clock information in a local network These procedures may be of interest to the designers and implementers of other local networks

Wire-routing machines—New tools for VLSI physical design

Abstract: Interconnection of components in a VLSI chip is becoming an increasingly complex problem. In this paper we examine the complexity of the wire routing process and discuss several new approaches to solving the problem using a parallel system architecture. The machines discussed range from compact systems for highly specialized applications to more general designs suited for broader applications. The process speedup due to parallelism and the cost advantage due to the use of large numbers of identical VLSI parts make these new machines practical today.

The Experimental Integrated Switched Network - a System-Level Network Test Facility

Abstract: An Experimental Integrated Switched Network (EISN) has been developed to provide a system-level testbed for the evaluation of advanced communications networking techniques, including survivable network routing algorithms using a mix of transmission media, for application in the Defense Switched Network (DSN). EISN includes five CONUS sites linked by a wideband demand-assigned satellite channel and by dialed-up terrestrial trunks for alternate satellite/terrestrial routing experiments. Experiments to date have validated techniques for integration of circuit-switched terrestrial systems with the demand-assigned satellite system, and for the establishment of alternate routes over satellite and terrestrial paths. Currently, candidate routing algorithms for application in the DSN are being implemented and tested using external routing/controller processors attached to digital circuit switches at EISN sites. In addition, EISN is also being used to support data communication experiments using DoD standard data protocols in a combined satellite/ terrestrial network environment. Work is ongoing both in system experiments and in testbed developments to include additional capabilities. This paper represents a description and status report on both the testbed and the experimental efforts.

Single-Layer Routing for VLSI: Analysis and Algorithms

Abstract: In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.

Automatic placement algorithms for high packing density V L S I

Abstract: Five placement procedures which combine three basic algorithms are developed and incorporated to our system. Evaluation of results is presented. Compared with manual design the optimum procedure reduces block size by 6.5%. The normalized area for one transistor (NA) is defined as the measure of automatic layout performance. NA is the product of wiring pitch. Optimum NA is confirmed to be 14.9 for manual design and 13.9 for automatic layout using the optimum procedure. This system is applicable to both custom logic LSIs and masterslice LSIs and has been applied to layouts of many such devices.

SNA routing: past, present, and possible future

Abstract: This paper reviews the evolution of routing mechanisms in IBM's Systems Network Architecture (SNA) since its inception in 1974 to the present. Routing mechanisms are related to changes in the application and communications environment. Also discussed are possible evolutionary paths that may be taken in the future to address the problems of large heterogeneous networks.