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Showing papers on "Routing (electronic design automation) published in 1987"


Journal ArticleDOI
TL;DR: A branch-and-bound method is described that minimizes the total route length in vehicle routing problems with time windows, and some computational results are presented.
Abstract: In vehicle routing problems with time windows, a fixed fleet of vehicles of limited capacity is available at a depot to serve a set of clients with given demands. Each client must be visited within a given time window. We describe a branch-and-bound method that minimizes the total route length, and present some computational results.

331 citations


Proceedings ArticleDOI
01 Oct 1987
TL;DR: The REAL REgister ALlocation program uses a track assignment algorithm taken from channel routing called the Left Edge algorithm to process designs output from MAHA and Sehwa, and is thought to be optimal for non-pipelined designs with no conditional branches.
Abstract: This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm taken from channel routing called the Left Edge algorithm. REAL is optimal for non-pipelined designs with no conditional branches. It is thought that REAL is also optimal for designs with conditional branches, pipelined or not. Experimental results are included in the report, which illustrate the optimal solutions found by REAL. REAL is part of the ADAM Advanced Design AutoMation system, and will be used to process designs output from MAHA and Sehwa.

324 citations


01 Feb 1987

277 citations


Journal ArticleDOI

229 citations


Proceedings ArticleDOI
Abhiram Ranade1
12 Oct 1987
TL;DR: In this paper, the authors presented a simple algorithm for emulating an N processor CRCW PRAM on an N node butterfly, where each step of the PRAM is emulated in time O(log N) with high probability, using FIFO queues of size O(1) at each node.
Abstract: We present a simple algorithm for emulating an N processor CRCW PRAM on an N node butterfly. Each step of the PRAM is emulated in time O(log N) with high probability, using FIFO queues of size O(1) at each node. The only use of randomization is in selecting a hash function to distribute the shared address space of the PRAM onto the nodes of the butterfly. The routing itself is both deterministic and oblivious, and messages are combined without the use of associative memories or explicit sorting. As a corollary we improve the result of Pippenger [8] by routing permutations with bounded queues in logarithmic time, without the possibility of deadlock. Besides being optimal, our algorithm has the advantage of extreme simplicity and is readily suited for use in practice.

215 citations


Journal ArticleDOI
TL;DR: The experimental results on examples with a large number of irregular blocks show that the new methodology out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less.
Abstract: A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in a special class of partial 3-trees, which can be solved optimally in linear time. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks show that our approach out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less. Due to the unique goal-oriented and pattern-directed features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design.

150 citations


Patent
17 Aug 1987
TL;DR: In this paper, the authors propose a logic circuit, available at every node, implements the algorithm and automatically forwards or back-tracks the header in the network legs of various paths until a completed path is latched.
Abstract: A circuit switching system in an M-ary, n-cube connected network completes a best-first path from an originating node to a destination node by latching valid legs of the path as the path is being sought out. Each network node is provided with a routing hyperswitch sub-network, ("HSN") connected between that node and bidirectional high capacity communication channels of the n-cube network. The sub-networks are all controlled by routing algorithms which respond to message identification headings ("headers") on messages to be routed along one or more routing legs. The header includes information embedded therein which is interpreted by each sub-network to route and historically update the header. A logic circuit, available at every node, implements the algorithm and automatically forwards or back-tracks the header in the network legs of various paths until a completed path is latched.

131 citations


Journal ArticleDOI
TL;DR: Recent research related to various modeling approaches for location/routing problems, including comprehensive mathematical programming formulations, analytical approximations, and modified facilitation approaches are discussed.
Abstract: SYNOPTIC ABSTRACTFacility location and vehicle routing are two widely used and studied management science resource planning models. According to the 1986 Statistical Abstract of the United States, freight transportation outlays for local trucking totaled 80.9 billion dollars in 1983. Thus, location/routing decisions have considerable economic importance in domains such as distribution systems planning. Since location and routing decisions are closely related, integrated models that consider the two aspects simultaneously offer the promise of more effective and economical decisions. However, such integrated models are complex and their design poses challenges in combining the short-term operational considerations of vehicle routing with the medium/long-term strategic issues of facility location. This paper discusses recent research related to various modeling approaches for location/routing problems, including comprehensive mathematical programming formulations, analytical approximations, and modified faci...

107 citations


Journal ArticleDOI
TL;DR: This paper presents a new routing technique that can be applied for general two-layer detailed routing problems, including switchboxes, channels, and partially routed areas, and has performed as well as or better than existing algorithms.
Abstract: For the macrocell design style and for routing problems in which the routing regions are irregular, two-dimensional routers are often necessary. In this paper, a new routing technique that can be applied for general two-layer detailed routing problems, including switchboxes, channels, and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear edges, the pins can be on or inside the boundaries of the region, and the obstructions can be of any shape and size. The technique is based on an algorithm that routes the nets in the routing region incrementally and intelligently, and allows modifications and rip-up of nets when an existing shortest path is "far" from optimal or when no path exists. The modification steps (also called weak modification) relocate some segments of nets already routed to find a shorter path or to make room for a blocked net. The rip-up and reroute steps (called strong modifiction) remove segments of nets already routed to make room for a blocked connection; these steps are invoked only if weak modification fails. The algorithm has been rigorously proven to complete in finite time and its complexity has been analyzed. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and on all the examples known in the literature the router has performed as well as or better than existing algorithms. In particular, Burstein's difficult switchbox example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II on all the channels available to us.

103 citations


Patent
Nakajima Yasuhiro1
07 Oct 1987
TL;DR: In this article, a routing method for wiring design including a determining step for identifying, in one of the wiring sections where no wiring path is determined as yet, the direction of the line segment which is prohibited by an obstacle and accordingly determining a wiring path.
Abstract: A routing method for wiring design including a determining step for identifying, in one of the wiring sections where no wiring path is determined as yet, the direction of the line segment which is prohibited by an obstacle and accordingly determining a wiring path. The routing method also includes a generating step for generating, on a layer opposite to the layer on which one unprocessed line segment is present and in a position having the same plane coordinates as the line segment, an obstacle which prohibits only such line segments as are parallel in direction to the line segment, on the wiring path determined by the determining step.

96 citations


Patent
13 Jul 1987
TL;DR: In this article, a static dataflow architecture of the type in which a plurality of data flow processing elements communicate externally by means of input/output circuitry (128), and internally by sending packets through a routing network (124) via paths.
Abstract: A novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of data flow processing elements (110) communicate externally by means of input/output circuitry (128), and internally by means of packets sent through a routing network (124) via paths (122). The routing network (124) implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions. In accordance with the present invention, these instructions include associations of execution components and enable components identified by instruction indices.

Patent
11 Mar 1987
TL;DR: In this paper, the source, destination and identity of a segment-in-process (SIP) is provided to the host computer system by a client process, and the host defines a sequence of distributed routing units through which the SIP will move from its source to its destination.
Abstract: Segments-in-process (SIPs) of material are automatically routed through a material handling system by distributed routing units under the guidance of a host computer system. The material handling system comprises a network of intersecting material paths. A distributed routing unit is located at material path intersections. Information relating to the source, destination and identity of a SIP is provided to the host computer system by a client process. Typically the destination of the SIP is a process machine located on a material path. Upon receipt of the information from the client process, the host defines a sequence of distributed routing units through which the SIP will move from its source to its destination. Each distributed routing unit in the sequence is then provided with information which enables each unit to identify the SIP and to perform a task with respect thereto. The tasks are then sequentially performed such that the SIP is routed through the defined sequence to its destination. The SIP may be routed to its destination when the host computer system is off line.

Proceedings ArticleDOI
01 Oct 1987
TL;DR: This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias and yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.
Abstract: This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias. The time complexity of the algorithm is O(n /sup 3/) where n is the number of routing segments in the given layout. Unlike previous algorithms, this algorithm does not require the layout to be grid based and places no constraints on the location of vias or the number of wires that may be joined at a single junction. The algorithm yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.

Patent
24 Jun 1987
TL;DR: In this article, a complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered, and each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution.
Abstract: An automated LSI chip layout arrangement includes automated layout of the power bus distribution network. A complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered. Each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution. If it can be removed, the segment is deleted. The next segment which is critical to the size of the chip is then tested, and the process is continued. Those segments of the power bus distribution network which do not affect the size of the chip are not eliminated. Thus, a low-resistance power distribution bus network is guaranteed, and chip size is minimized.

Proceedings ArticleDOI
01 Oct 1987
TL;DR: Algorithms in a printed circuit board router used for fully automatic routing of high-density circuit boards have resulted from a new data structure for efficient representation of the routing grid, quick searches for optimal solutions, and generalizations of Lee's algorithm.
Abstract: This paper describes the algorithms in a printed circuit board router used for fully automatic routing of high-density circuit boards. Completely automatic routing and running times of a few minutes have resulted from a new data structure for efficient representation of the routing grid, quick searches for optimal solutions, and generalizations of Lee's algorithm.

Journal ArticleDOI
TL;DR: A router based on a tile-expansion algorithm and corner stitching data structure is presented that finds connections with a minimum number of jogs and it ensures that a possible solution will be found.
Abstract: A router based on a tile-expansion algorithm and corner stitching data structure is presented. This program finds connections with a minimum number of jogs and it ensures that a possible solution will be found. Using a working tree, it allows an exhaustive and recursive search along all available areas for routing. The connections are made going back through the working tree until the starting terminal is reached. There are two Manhattan layers that the user can choose for each direction to implement connections; the router can be used to wire hierarchical blocks using a chip planning methodology. The program has been successfully tested on examples concerning different classes of problems.


Patent
20 Oct 1987
TL;DR: In this article, a switch fabric consisting of parallel equal switching slices, e.g., binary routing trees, is used to transfer each minipacket from its input port to one output port in response to the routing address.
Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i) The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port The switch fabric consists of parallel equal switching slices, eg binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports

Patent
24 Aug 1987
TL;DR: In this paper, the window manager may modify the routing table and all keycodes remaining in the buffer are routed to their associated processes as determined by the modified routing table, unless otherwise indicated, a keycode is routed to the active process.
Abstract: A computer system in which multiple processes may run concurrently includes a window manager for displaying windows associated with different processes. One of the processes represented by a window may be designated as active. Keystrokes are translated by a keyboard driver to events represented by keycodes. The keycodes are routed to processes with which they are associated by reference to a routing table. Unless otherwise indicated, a keycode is routed to the active process. Where a keycode is associated with and transferred to the window manager, subsequent keycodes are stored in a typeahead buffer. The window manager may modify the routing table. After completion of the window manager operation, all keycodes remaining in the buffer are routed to their associated processes as determined by the modified routing table.

Proceedings ArticleDOI
01 Oct 1987
TL;DR: Experimental results show that both approaches for the L-shaped channel-routing problem provide good solutions, and all the vertical constraints substituted by 45° constraints can be directly mapped into the straight-type channels problem.
Abstract: The concept of L-shaped channels was first introduced in RRDO [1] to generate a feasible routing order for nonslicing-structure placement in building-block layout design. This paper presents two approaches for the L-shaped channel-routing problem. In the Manhattan approach, only horizontal and vertical wires are used. The L-shaped channel is divided into two subchannels. The vertical subchannel will be routed first, then the horizontal subchannel will be routed by a special channel router which can handle fixed terminals on 3 sides. Since the routing constraints will change during the boundary movement, several iterations may be needed to complete the routing. In the non-Manhattan approach, 45 ° wires are used to preserve the routing constraints when the boundary is moved in the 45 ° direction. With all the vertical constraints substituted by 45 ° constraints, the L-shaped channel-routing problem can be directly mapped into the straight-type channel-routing problem. Horizontal or vertical extension wires are used to connect terminals on an indented boundary and to separate terminals which are too close to allow the generation of 45 ° wires. Experimental results show that both approaches provide good solutions to the L-shaped channel-routing problem.

Journal ArticleDOI
TL;DR: Using the number of time intervals required for a node to recover from a network failure as the measure of network's adaptability, performance of this strategy and the ARPANET's previous routing strategy is comparatively analyzed without resorting to simulation.
Abstract: This paper deals with a distributed adaptive routing strategy which is very simple and effective, and is free of a ping-pong-type looping in the presence of network failures. Using the number of time intervals required for a node to recover from a network failure as the measure of network's adaptability, performance of this strategy and the ARPANET's previous routing strategy (APRS) is comparatively analyzed without resorting to simulation. Formulas of the exact number of time intervals required for failure recovery under both strategies are also derived. We show that i)the performance of the strategy is always better than, or at least as good as, that of APRS, and ii) network topology has significant effects on the performance of both strategies.

Proceedings ArticleDOI
Bryan T. Preas1
01 Oct 1987
TL;DR: The benefits, problems and challenges of creating, distributing and maintaining a representative set of benchmarks for cell-based layout systems are considered.
Abstract: Introduction Cell-based layout systems are widely used for automatic physical design of large digital systems. Standard cell and gate array layout systems are reaching a state of maturity: small differences in layout effectiveness are used to distinguish commercially available systems. General cell and mixed standard cell and general cell layout systems have moved from research projects to general availability. Even with this widespread use and the many publications of cell-based layout systems, no recognized benchmarks are available to form the basis of comparison and evaluation. In addition to the difficulty of comparing layout systems, algorithm research is hampered by the lack of recognized benchmark examples. It is very difficult to evaluate published algorithms because common examples are not used. Potentially promising algorithms have been denied publication because some researchers do not have access to real circuit descriptions. Random or contrived examples are, to a large number of reviewers, no longer acceptable for journal and conference publication. For some problems, publication of examples is sufficient to establish industry wide benchmarks; channel and switchbox routing are examples. However, cell-based layout problems are much too complex for such casual methods. Practical circuits may have several thousand cells, and circuits with over 10,000 cells are reported with some regularity. For such circuits, the parts list and the interconnection list may require a substantial fraction of a megabyte for storage. In addition to large size, the complexity of the cell libraries and the design rules inhibit sharing of layout examples. This panel wiH consider the benefits, problems and challenges of creating, distributing and maintaining a representative set of benchmarks for cell-based layout systems.

Journal ArticleDOI
TL;DR: In this paper, the authors describe two types of rail transportation problems in detail: train routing and makeup, and empty car distribution problems, and some of the recent optimization models which address these problems are reviewed.
Abstract: This paper describes two types of rail transportation problems in detail. These are train routing and makeup, and empty car distribution problems. Some of the recent optimization models which address these problems are reviewed and the areas for potential improvements in rail transportation literature are identified. The type of interactions which exist between routing, makeup, and empty car distribution decisions are highlighted and potential areas for future research are identified.


Journal ArticleDOI
TL;DR: In this article, a flexible manufacturing system FMS is modeled as a closed queueing network with a set of stations, each with a local buffer of limited capacity, and the authors derive product-form solutions to a class of such FMS networks that have reversible parts routing a system with a centralized material handling station.
Abstract: We model a flexible manufacturing system FMS as a closed queueing network with a set of stations, each with a local buffer of limited capacity. Based on the theory of reversibility as well as some known approaches in the studies of queueing networks with finite buffers, we derive product-form solutions to a class of such FMS networks that have reversible parts routing a system with a centralized material handling station being one example. This class also includes a certain type of dynamic routing scheme. For systems with zero-buffer stations, we show that the solutions have product form even for nonexponential processing times.

Journal ArticleDOI
01 Dec 1987
TL;DR: A model of a nonstationary automaton environment, with response characteristics dynamically related to the probabilities of the actions performed on it, is proposed and parameters of the proposed model can be chosen to predict transient behavior.
Abstract: In a data communication network the message traffic has peak and slack periods and the network topology may change. When the learning approach is applied to routing, a learning automation is situation at each node in the network. Each automation selects the routing choices at its node and modifies its strategy according to network conditions. A model of a nonstationary automaton environment, with response characteristics dynamically related to the probabilities of the actions performed on it, is proposed. The limiting behavior of the model is identical to that of the earlier models. Simulation studies of automata operating in simple queuing networks reinforce the analytical results and show that the parameters of the proposed model can be chosen to predict transient behavior.

Journal ArticleDOI
Y. Shiraishi1, J. Sakemi
TL;DR: A permeation routing algorithm is proposed which decides the detailed routes on a new layout model and attains a higher density by using the expanded routing region as well as the conventional one simultaneously.
Abstract: A permeation routing algorithm is proposed which decides the detailed routes on a new layout model. The permeation router attains a higher density by using the expanded routing region as well as the conventional one simultaneously. This routing algorithm consists of two phases. One is to partition the trunk set into three subsets corresponding to the trunks to be routed in the channel on the lower transistor row, upper transistor row, or between transistor rows. The other is to route these channels by using the one-layer channel assignment method as well as the conventional one. The experiments show that the routing results are practical and that the processing time is proportional to the number of trunks to the power of 1.4.

Journal ArticleDOI
W.K. Luk1, P. Sipala, M. Tamminen, D. Tang, L. S. Woo, C. K. Wong 
TL;DR: A global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model), which is implemented in the C language and used for chip designs.
Abstract: We present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. The worst-case run-time for an arbitrary slicing tree (totally skewed) is O(M /sup 2/ N). When the floorplan is represented by a balanced slicing tree, the run-time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and is used for chip designs. Experiments on both real and randomly generated designs show that the hierarchical router performs equally well as a flat global router in terms of wire length and wireability handling, but much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger-size problems).

Patent
29 Jun 1987
TL;DR: In this paper, an optical interconnect structure for routing and distributing optical signals on silicon chip carriers is proposed to realize high-density packaged optical interfaces for discrete GaAs optoelectronic IC's.
Abstract: This invention discloses an optical interconnect structure for routing and distributing optical signals on silicon chip carriers to realize high-density packaged optical interconnects for discrete GaAs optoelectronic IC's.

Journal ArticleDOI
TL;DR: It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.
Abstract: A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.