Showing papers on "Routing (electronic design automation) published in 1988"

Routing of multipoint connections

Abstract: The author addresses the problem of routing connections in a large-scale packet-switched network supporting multipoint communications. He gives a formal definition of several versions of the multipoint problem, including both static and dynamic versions. He looks at the Steiner tree problem as an example of the static problem and considers the experimental performance of two approximation algorithms for this problem. A weighted greedy algorithm is considered for a version of the dynamic problem which allows endpoints to come and go during the life of a connection. One of the static algorithms serves as a reference to measure the performance of the proposed weighted greedy algorithm in a series of experiments. >

Programming a computer for playing chess

Abstract: This paper is concerned with the problem of constructing a computing routine or “program” for a modern general purpose computer which will enable it to play chess. Although perhaps of no practical importance, the question is of theoretical interest, and it is hoped that a satisfactory solution of this problem will act as a wedge in attacking other problems of a similar nature and of greater significance. Some possibilities in this direction are:- (1) Machines for designing filters, equalizers, etc. (2) Machines for designing relay and switching circuits. (3) Machines which will handle routing of telephone calls based on the individual circumstances rather than by fixed patterns. (4) Machines for performing symbolic (non-numerical) mathematical operations. (5) Machines capable of translating from one language to another. (6) Machines for making strategic decisions in simplified military operations. (7) Machines capable of orchestrating a melody. (8) Machines capable of logical deduction.

Multicast routing in internetworks and extended LANs

Abstract: Multicasting is used within local-area networks to make distributed applications more robust and more efficient. The growing need to distribute applications across multiple, interconnected networks, and the increasing availability of high-performance, high-capacity switching nodes and networks, lead us to consider providing LAN-style multicasting across an internetwork. In this paper, we propose extensions to two common internetwork routing algorithms—distance-vector routing and link-state routing—to support low-delay datagram multicasting. We also suggest modifications to the single-spanning-tree routing algorithm, commonly used by link-layer bridges, to reduce the costs of multicasting in large extended LANs. Finally, we show how different link-layer and network-layer multicast routing algorithms can be combined hierarchically to support multicasting across large, heterogeneous internetworks.

The landmark hierarchy: a new hierarchy for routing in very large networks

Abstract: Landmark Routing is a set of algorithms for routing in communications networks of arbitrary size. Landmark Routing is based on a new type of hierarchy, the Landmark Hierarchy. The Landmark Hierarchy exhibits path lengths and routing table sizes similar to those found in the traditional area or cluster hierarchy. The Landmark Hierarchy, however, is easier to dynamically configure using a distributed algorithm. It can therefore be used as the basis for algorithms that dynamically configure the hierarchy on the fly, thus allowing for very large, dynamic networks. This paper describes the Landmark Hierarchy, analyzes it, and compares it with the area hierarchy.

Method and apparatus for routing communications among computer networks

Abstract: An improved method and apparatus for routing data transmissions among computer networks. The computer networks are interconnected with a series of gateway circuits. Each gateway identifies all destination computers to which it is connected and identifies the path or paths to each destination computer. For each identified path, the gateway stores the topological delay time for a transmission, the path bandwidth for the narrowest bandwidth segment of a path and a number corresponding to the reliability of the path. When a transmission is received, the gateway examines the various paths in accordance with a predetermined algorithm which also considers the channel occupancy of each path to determine a best path for transmision. The data transmission is then directed over the best path. If more than one path exists, the data may be directed in multiplex fashion over two or more paths with the amount of data on each path being related to the quality of the path. The routing information to destination networks is broadcast periodically by each gateway circuit to its neighboring gateway circuits.

Vehicle routing with time windows: optimization and approximation. vehicle routing: method and studies. studies in management science and systems - volume 16

Abstract: This is a survey of solution methods for routing problems with time window constraints. Among the problems considered are the traveling salesman problem, the vehicle routing problem, the pickup and delivery problem, and the dial-a-ride problem. We present optimization algorithms that use branch and bound, dynamic programming and set partitioning, and approximation algorithms based on construction, iterative improvement and incomplete optimization. (Author/TRRL)

Routing in circuit-switched networks: optimization, shadow prices and decentralization

Abstract: How should calls be routed or capacity allocated in a circuit-switched communication network so as to optimize the performance of the network? This paper considers the question, using a simplified analytical model of a circuit-switched network. We show that there exist implicit shadow prices associated with each route and with each link of the network, and that the equations defining these prices have a local or decentralized character. We illustrate how these results can be used as the basis for a decentralized adaptive routing scheme, responsive to changes in the demands placed on the network.

Method and apparatus for routing message packets

Abstract: A message packet router (130) is described that performs the functions of determining if a message packet is addressed to circuitry associated with the router (130), of routing message packets to their destination if possible and of storing message packets that cannot be routed on because of circuit conflicts. The router (130) also provides additional functions of merging message packets addressed to the same destination, of saving the state of the router (130) at each significant point in the message routing cycle, and of running the entire routing cycle backwards. This later feature makes it possible to broadcast message packets selectively to certain processors (112) in the array.

Vehicle routing with time windows: Optimization and approximation

Abstract: A survey of solution methods for routing problems with time window constraints. Among the problems considered are the traveling salesman problem, the vehicle routing problem, the pickup and delivery problem, and the dial-a-ride problem. Optimization algorithms that use branch and bound, dynamic programming and set partitioning, and approximation algorithms based on construction, iterative improvement and incomplete optimization are presented.

The constrained via minimization problem for PCB and VLSI design

Abstract: A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed. >

Heuristics Based on Spacefilling Curves for Combinatorial Problems in Euclidean Space

Abstract: We describe a family of heuristics to solve combinatorial problems such as routing and partitioning. These heuristics exploit geometry but ignore specific distance measures. Consequently they are simple and fast, but nonetheless fairly accurate, and so seem well-suited to operational problems where time or computing resources are limited. We survey promising new application areas, and show how procedures may be customized to reflect the structure of particular applications.

Multiprocessor digital data processing system

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells (18A to 18R, 34A to 34F, 38A, 38B) arranged in a hierarchy of rings (12A to 12F, 14A and 14B, 16). The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Multihop lightwave networks: a new approach to achieve terabit capabilities

Abstract: A multihop approach for achieving concurrency in distributed lightwave networks with hundreds or thousands of Gb/s throughput, even while the users are limited to rates of 1 Gb/s or lower, is described. Multihop networks avoid two serious drawbacks of standard multichannel approaches: the requirement of wavelength-agile transmitters or receivers, and pretransmission coordination between users wishing to communicate. Although transmitting a packet from one user to another may require routing the packet through intermediate network interface units, the approach's connectivity is specifically designed to achieve efficient use of the channel bandwidth, allow modular growth of the network from small to large configurations, and provide a degree of network reliability. >

Multiple spot-beam systems for satellite communications

Abstract: On-board satellite switching is performed in three stages, an outer stage of switching on the up-link side for routing the received signals to either demodulators or frequency translators, a first inner stage of switching, preferably a baseband switch and processor, for routing and processing the outputs of the demodulators, a second inner stage of switching, e.g., a microwave switch matrix, for routing the outputs of the frequency translators, and an outer stage on the down-link side for assembling and routing the down-link spot beams. For a multiple hopping-beam system, the outer stages are microwave switch matrices, and for a hybrid scanning-hopping system the outer stages are beam forming matrices. A general purpose modified rearrangeable switch matrix is also disclosed.

Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing

Abstract: The algorithms and the implementation of a new macro/custom cell chip-planning, placement, and global routing package are presented. The simulated-annealing-based placement algorithm proceeds in two stages. In the first stage, the interconnect area around the individual cells is determined using a new dynamic interconnect area estimator. The second stage consists of: (1) a channel definition step, using a new channel definition algorithm, (2) a global routing step, using a new global router algorithm, and (3) a placement refinement step. This strategy has produced placements which require very little placement modification during detailed routing. Total interconnect length savings of 8 to 49 percent were achieved in experiments on 9 industrial circuits. Furthermore, circuit-area reductions ranged from 4 to 56 percent versus a variety of other placement methods.

Dynamic Scheduling and Routing for Flexible Manufacturing Systems that Have Unreliable Machines

Abstract: This paper presents a method for real-time scheduling and routing of material in a Flexible Manufacturing System FMS. It extends the earlier scheduling work of Kimemia and Gershwin in which the FMS model includes machines that fail at random times and stay down for random lengths of time. The new element is the capability of different machines to perform some of the same operations. The times that different machines require to perform the same operation may differ. This paper includes a model, its analysis, a real-time algorithm, and examples.

Dynamic Alternative Routing - Modelling and Behaviour

Abstract: DAR, dynamic alternative routing, is a simple but effective form of dynamic routing which is decentralised and which uses only a small amount of local information. This paper examines the modelling and behaviourial aspects of such a scheme. In particular various bounds are presented which hold for any kind of dynamic routing scheme, and can be used to assess the performance of DAR. DAR can be investigated by a simple analytical model, of familar fixed-point form, and simulation studies have verified its accuracy. A simple form of dimensioning is mentioned, and methods of setting trunk reservation parameters are discussed. These are necessary both to improve performance and prevent instability. Lastly, simple ways of extending DAR are examined.

A new area and shape function estimation technique for VLSI layouts

Abstract: Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. This paper describes a new model for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks and for the placement of general cells.Categories: 6, 9

ILAC: an automated layout tool for analog CMOS circuits

Abstract: A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD (computer-aided design) tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations. ILAC is the companion tool of IDAC, a design tool that sizes analog CMOS circuits from a library of proven schematics given a set of functional specifications and technological parameters. Unlike existing analog silicon compilers that use some predefined placement for a specific type of circuit, ILAC determines an optimal layout for any circuit and any set of input parameters. >

Telecommunications switching system

Abstract: A switching system is described in which routing information, which may be associated with packets originating in cellular calls, is divided into information which does not change as the subscriber crosses a cell boundary, and information which does change as the subscriber crosses a cell boundary. Routing procedures associated with the information which does not change as the subscriber crosses a cell boundary are established and stored in the memory of the switch at the beginning of the call. However, routing procedures associated with the information which does change as the subscriber crosses a cell boundary may be derived from the header information of each packet as it arrives at the appropriate portion of the switch.

A new global router for row-based layout

Abstract: A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed. It is part of the latest version of TimberWolfSC, a placement and routing package for row-based layout. The algorithm outperformed the UTMC Highland system on two standard benchmark circuits. In tests on ten circuits, the global router produced track counts which were an average of 27% lower than those of the previous TimberWolfSC global router. The router is an average of 30 times faster than the previous algorithm. It has been generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Indiscriminate over-the-cell routing is also handled. >

Over-the-cell channel routing

Abstract: A common approach to the over-the-cell channel routing problem is to divide the problem into three steps: (1) routing over the cells; (2) choosing net segments; and (3) routing within the channel. It is shown that the first step can be reduced to the problem and finding a maximum independent set of a circle graph, and thus can be solved optimally in quadratic time. Also, it is shown that to determine an optimal choice of net segments in the second step is NP-hard in general, and an efficient heuristic algorithm for this step is presented. The third step can be carried out using a conventional channel router. On the basis of these theoretical results, an over-the-cell channel router that produces solutions which are better than the optimal two-layer channel routing solutions for all test examples is designed. The over-the-cell channel router also outperforms the over-the-cell channel router described by Y. Shiraishi and Y. Sakemi (ibid., vol.CAD-6, no.3, p.462-71, 1987). In particular, for Deutsch's difficult example, the solution yields a saving of 10.5% in channel routing area when compared with the optimal two-layer channel routing solution, and a saving of 15% in channel routing area when compared with the routing solution produced by the over-the-cell channel router. >

Vehicle routing with site dependencies. vehicle routing: methods and studies. studies in management science and systems - volume 16

Abstract: Given a vehicle routing problem with a heterogeneous fleet, suppose that each site can be serviced by some, but not necessarily all, vehicle types. Customers with high demands may require large vehicles. Others in congested areas may require small or medium vehicles. In this paper, we analyze several heuristics for solving this variant of the vehicle routing problem where the incompatibility of customer sites with certain vehicle types acts as a complicating constraint. (Author/TRRL)

Communication-efficient parallel algorithms for distributed random-access machines

Abstract: This paper introduces a model for parallel computation, called thedistributed randomaccess machine (DRAM), in which the communication requirements of parallel algorithms can be evaluated. A DRAM is an abstraction of a parallel computer in which memory accesses are implemented by routing messages through a communication network. A DRAM explicitly models the congestion of messages across cuts of the network. We introduce the notion of aconservative algorithm as one whose communication requirements at each step can be bounded by the congestion of pointers of the input data structure across cuts of a DRAM. We give a simple lemma that shows how to "shortcut" pointers in a data structure so that remote processors can communicate without causing undue congestion. We giveO(lgn)-step, linear-processor, linear-space, conservative algorithms for a variety of problems onn-node trees, such as computing treewalk numberings, finding the separator of a tree, and evaluating all subexpressions in an expression tree. We giveO(lg2n)-step, linear-processor, linear-space, conservative algorithms for problems on graphs of sizen, including finding a minimum-cost spanning forest, computing biconnected components, and constructing an Eulerian cycle. Most of these algorithms use as a subroutine a generalization of the prefix computation to trees. We show that any suchtreefix computation can be performed inO(lgn) steps using a conservative variant of Miller and Reif's tree-contraction technique.

Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays

Abstract: Systems of linear recurrences are a very powerful means for specifying algorithms that need to be implemented on a systolic array or, more generally, on a parallel architecture. In particular, the class of linear recurrences called uniform recurrences can be mapped automatically on systolic arrays. However, it is often difficult to express the algorithm directly using strictly uniform recurrences, especially when the algorithm involves recursive computations, as in the transitive closure problem. Novel tools for the uniformization of linear recurrences are provided. Their use is illustrated by solving the so-called routing problem, which is a particular uniformization problem. Two routing strategies are presented, namely, hierarchical routing and split routing. >

Dynamic vehicle routing problems. vehicle routing: methods and studies. studies in management science and systems - volume 16

Abstract: The purpose of this paper is to put dynamic vehicle routing into perspective within the broader area of vehicle routing, as well as provide a flavor of recent progress in this area. We identify the important issues that delineate the dynamic case vis-a-vis the static one, comment on methodological issues, review generic design features that a dynamic vehicle routing procedure should possess, discuss the adaptation of static approaches to a dynamic setting, and describe an algorithm for the dynamic routing of cargo ships in an emergency situation. We conclude by recommending directions for further research in this area. (Author/TRRL)

Laser programmable integrated circuit

Abstract: A laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns. The modules and other chip components are connected by a grid-like array of conductors. The conductors are initially unattached. Customization occurs by fusing laser diffuseable links and severing cut points on the conductors. The modules have continuous conductor lines running through them. These conductor lines aid in testing and are useful in routing and error avoidance. The chip also contains test registers to test the array of logic modules, the input/output blocks, and the conductors.

Optimum design of IC power/ground nets subject to reliability constraints

Abstract: The authors formulate and solve the problem of sizing power/ground (p/g) nets in integrated circuits composed of modules, where the nets are routed as trees in the channels between the modules. Constraints are developed to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule requirements. The objective is to minimize the area of the p/g nets subject to these constraints. An optimization technique tailored to this problem is developed. The technique solves the problem more efficiently than the steepest descent method and Newton's method. Several case studies are presented. >