Showing papers on "Routing (electronic design automation) published in 1989"

A trade-off between space and efficiency for routing tables

Abstract: Two conflicting goals play a crucial role in the design of routing schemes for communication networks. A routing scheme should use paths that are as short as possible for routing messages in the network, while keeping the routing information stored in the processors' local memory as succinct as possible. The efficiency of a routing scheme is measured in terms of its stretch factor-the maximum ratio between the length of a route computed by the scheme and that of a shortest path connecting the same pair of vertices.Most previous work has concentrated on finding good routing schemes (with a small fixed stretch factor) for special classes of network topologies. In this paper the problem for general networks is studied, and the entire range of possible stretch factors is examined. The results exhibit a trade-off between the efficiency of a routing scheme and its space requirements. Almost tight upper and lower bounds for this trade-off are presented. Specifically, it is proved that any routing scheme for general n-vertex networks that achieves a stretch factor k ≥ 1 must use a total of O(n1+1/(2k+4)) bits of routing information in the networks. This lower bound is complemented by a family K(k) of hierarchical routing schemes (for every k ≥ l) for unit-cost general networks, which guarantee a stretch factor of O(k), require storing a total of O(k3n1+(1/h)logn)- bits of routing information in the network, name the vertices with O(log2n)-bit names and use O(logn)-bit headers.

Vehicle Routing with Stochastic Demands: Properties and Solution Frameworks

Abstract: This paper considers the vehicle routing problem with stochastic demands. The objective is to provide an overview of this problem, and to examine a variety of solution methodologies. The concepts and the main issues are reviewed along with some properties of optimal solutions. The existing stochastic mathematical programming formulations are presented and compared and a new formulation is proposed. A new solution framework for the problem using Markovian decision processes is then presented.

Message routing system for shared communication media networks

Abstract: A plurality of disparate communication network systems communicate with each other through the use of different physical media protocols. Each of the systems has at least one input and one output. A message routing system couples a transmitter at any one system input to a receiver at any other system output using a message format that is structure independent of the location of the receiver in the system. Each receiver/transmitter device coupled to any one system input has a unique, fixed and unchangeable identification code regardless of the communication network system to which it is connected. To couple a message from any one receiver/transmitter device to a second receiver/transmitter device at an unknown location within the communication network system, a message format is transmitted from the sending location containing the fixed, unique identification code of the receiving station. A routing system having a plurality of intermediate routing devices receives the message format and couples it to the receiving station at the unknown location using only the fixed, unique identification codes of the transmitting and receiving stations and the addresses of the intermediate routing devices for determining routing.

The revised ARPANET routing metric

Abstract: The ARPANET routing metric was revised in July 1987, resulting in substantial performance improvements, especially in terms of user delay and effective network capacity. These revisions only affect the individual link costs (or metrics) on which the PSN (packet switching node) bases its routing decisions. They do not affect the SPF (“shortest path first”) algorithm employed to compute routes (installed in May 1979). The previous link metric was packet delay averaged over a ten second interval, which performed effectively under light-to-moderate traffic conditions. However, in heavily loaded networks it led to routing instabilities and wasted link and processor bandwidth.The revised metric constitutes a move away from the strict delay metric: it acts similar to a delay-based metric under lightly loads and to a capacity-based metric under heavy loads. It will not always result in shortest-delay paths. Since the delay metric produced shortest-delay paths only under conditions of light loading, the revised metric involves giving up the guarantee of shortest-delay paths under light traffic conditions for the sake of vastly improved performance under heavy traffic conditions.

A system for routing and capacity assignment in computer communication networks

Abstract: The combined problem of selecting a primary route for each communicating pair and a capacity value for each link in computer communication networks is considered. The network topology and traffic characteristics are given: a set of candidate routes and of candidate capacities for each link are also available. The goal is to obtain the least costly feasible design where the costs include both capacity and queuing components. Lagrangean relaxation and subgradient optimization techniques were used to obtain verifiable solutions to the problem. The method was tested on several topologies, and in all cases good feasible solutions, as well as tight lower bounds, were obtained. The model can be generalized to deal with different classes of customers, characterized by different priorities, message lengths, and/or delay requirements. >

Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays

Abstract: A structure and method for producing mask-configured integrated circuits which are pin compatible substitutes for user-configured logic arrays is disclosed. Mask-defined routing lines having resistive/capacitive characteristics simulating those of user-configurable routing paths in the user-configurable logic array are used in the mask-defined substitutes to replace the user-configurable routing paths. Scan testing networks are formed in the metal-configured substitutes to test the operability of logical function blocks formed on such chips. The scan testing networks comprise a plurality of test blocks each including three field effect pass transistors formed of four adjacent diffusion regions. Proper connection of the gates of these pass transistors to control lines controlling the transistors is tested by transmitting alternating high/low signals through serial conduction paths including the gate electrodes of these transistors.

Directional information system

Abstract: The present invention relates to a method and system for enabling a user to determine a desired geographical route between supplied locations. To this end, a means is employed for supplying to a central processor information identifying geographic locations. The central processor, after correlating the identifying information to geographic locations, generates routing directions for travel between the two locations. The routing directions are made available for outputting to the user through a plurality of output devices.

A set‐partitioning‐based exact algorithm for the vehicle routing problem

Abstract: In this paper, we discuss a computationally viable algorithm based on a set-partitioning for-mulation of the Vehicle Routing Problem (VRP). Implementation strategies based on theoretical as well as empirical results are developed. Some computational results are presented. It is shown that a set-partitioning formulation to the VRP, although well known for a long time, deserves considerable research efforts beyond those we present here.

Formulation and solution of a combined train routing and makeup, and empty car distribution model

Abstract: This paper presents the formulation and solution of a combined train routing and makeup, and empty car distribution model. This formulation results in a large scale mixed-integer programming problem with nonlinear objective function and linear constraints. A heuristic decomposition technique is developed to solve the model. This solution procedure exploits the special structure of the problem and decomposes it into smaller subproblems based on the type of decision variables. Model testing results are also presented.

A composite algorithm for a concave‐cost network flow problem

Abstract: We consider the problem of routing multiple commodities between various origin—destination pairs in a network, at minimum total cost. Economies of scale in arc flow costs are modeled using piecewise linear, concave total-cost functions for each arc. This model applies to a variety of medium- and long-term planning contexts including transportation planning, design of communication networks, plant location and capacity expansion planning, production planning, and water resource management. We formulate the general problem as a mixed-integer program and develop a composite algorithm to generate both good lower bounds and heuristic solutions. We also report on computational results for several randomly generated general networks (with up to 40 nodes, 359 arcs, and 60 commodities) and layered neetworks (with up to 60 nodes, 372 arcs, and 60 commodities). These tests demonstrate that even for relatively large problems, the composite algorithm is very effective in generating solutions with small gaps between the upper and lower bounds (1.7% on average for general networks, and 0.4% on average for layered networks); for 19 out of the 25 layered network problems, the method generated and verified the optimal solution.

A 2n-2 step algorithm for routing in an nxn array with constant size queues

Abstract: In this paper we describe a deterministic algorithm for solving any 1–1 packet-routing problem on ann ×n mesh in 2n−2 steps using constant-size queues. The time bound is optimal in the worst case. The best previous deterministic algorithm for this problem required time 2n+Θ(n/q) using queues of size Θ(q) for any 1≤q≤n, and the best previous randomized algorithm required time 2n+Θ(logn) using constant-size queues.

An O(logN) deterministic packet routing scheme

Abstract: We present a deterministic O(log N) time algorithm for the problem of routing an arbitrary permutation on an N-processor bounded-degree network with bounded buffers.Unlike all previous deterministic solutions to this problem, our routing scheme does not reduce the routing problem to sorting and does not use the Ajtai, Komlos and Szemeredi sorting network [AKS]. Consequently, the constant in the run time of our routing scheme is substantially smaller, and the network topology is significantly simpler.

An economical scan design for sequential logic test generation

Abstract: A method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit is presented. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles to reduce sequential depth. Tests for the resulting circuit can be efficiently generated by a sequential logic test generator. An independent control of the scan clock allows the insertion of scan sequences within the vector sequence produced by the test generator. Experimental results on a 5000 gate circuit show that a test coverage above 98% could be obtained by scanning just 5% of the flip-flops. In addition, the authors give the design of a scan flip-flop to reduce the input pin and signal routing overheads in a single-clock design. >

Performance of a broadcast packet switch

Abstract: The results of a simulation study undertaken to evaluate a high-performance packet-switching fabric supporting point-to-point and multipoint communications are presented. This switching fabric contains several components, each based on conventional binary routing networks. The most novel element is the copy network, which performs the packet replication needed for multipoint connections. Results characterizing the performance of the copy network are presented. Several architectural alternatives for conventional binary routing networks are also evaluated. For example, the performance gains obtainable by using cut-through switching in the context of binary routing networks with small buffers are quantified. One surprising result is that networks constructed from nodes with more then two input and output ports can perform less well than those constructed from binary nodes. This result is quantified and explained. >

Multi‐Objective Programming Approach for Routing Hazardous Materials

Abstract: This paper examines the systemwide routing, of hazardous materials as a means of reducing the threat to the population residing along the links of an entire transportation network. A multi‐objective decision‐making model is used for the mathematical formulation of the routing problem. The proposed model includes the following objectives: (1) Minimization of risk; (2) minimization of risk of special population categories; (3) minimization of travel time; and (4) minimization of property damages. A capacitated and a noncapacitated version of the multiobjective routing problem are presented. A hypothetical network is used to display the applicability of the proposed model. For the example under consideration it is shown that the imposition of capacity constraints on the links of the network tends to distribute the risk in an equitable manner while it increases the total risk by 35%.

SILK: a simulated evolution router

Abstract: The authors present a rip-up-and-rerouter based on a matrix representation scheme and simulated evolution technique for solving detailed routing problems in VLSI layout. The status of the routing region is represented as a matrix. Rip-up and reroute operations are emulated as matrix subtractions and additions, respectively. The quality of a routing result can be measured by a few simple matrix operations on the matrix. A rip-up and reroute switch-box/channel router, called SILK, using a simulated evolution technique has been implemented based on this representation alone. Experimental results showed that SILK, when solving all the benchmarks from the literature, outperformed WEAVER, the most successful switch-box router to date, in both quality and speed aspects. >

Analysis of a flow problem with fixed charges

Abstract: This article addresses a problem that comes up frequently in network design, and routing. A source is to distribute flows to nodes in the network. Sending flow along an arc involves a fixed cost for using the arc and a variable cost for each ujnit of flow. We show tht the problem of finding a minimum cost collection of arcs along which flows will be directed is an NP-hard problem. We describe a procedure of solving the problem to optimality and several heuristics. In particular, we conclude that the use of polynomially derived Lagrange multipliers yields good quality solutions and bounds and can be implemented in a distributed processing mode in the network.

Interconnection length estimation for optimized standard cell layouts

Abstract: An accurate model for the prediction of interconnection lengths for standard cell layouts is presented. On the designs in the test suite estimates are within 10% of the actual layouts. The model abstracts the important features of placement, global routing, and channel routing. The predicted results are obtained from analysis of the net list. No prior knowledge of the functionality of the design is used. Accurate prediction of the interconnection length is useful for estimating the actual layout area, for evaluating the fit of a logic design to a fabrication technology, and for solving placement and routing algorithms. >

Machine process for routing interconnections from one module to another module and for positioning said two modules after said modules are interconnected

Abstract: In the present disclosure, a method of routing interconnections between a semiconductor module and another semiconductor module in a planar field by the use of a digital computer program is disclosed. The method is a variation of the prior art YACR method. The method provides for variable width track routing, as well as cost equation for net assignment and cost equation of net chosen to particular a horizontal track. The present invention also relates to a method for positioning the modules. The method of positioning the two modules or compacting the modules is a method for moving tracks between modules from one module to the other module as close to the opposite module as possible within the design rule constraints. The tracks are then moved in an opposite direction and the straightest segment to minimize jogs is chosen. Each track is then moved in the opposite direction and is moved as close to the straightest previous adjacent track as possible, within the design rule constraint.

Fault-tolerant routing in multistage interconnection networks

Abstract: The fault tolerance of multiprocessor systems with multistage interconnection networks under multiple faults in the network is studied. The fault tolerance is analyzed with respect to the criterion of dynamic full access (DFA) property of the processors in the system. A characterization of multiple faults in the Omega network is introduced and used to develop simple tests for the DFA capability under a given set of faults. It is shown that the DFA capability is maintained under a large number of faults. A maximum of three passes is shown to be sufficient for communication between any two processors in the system when the faults satisfy certain conditions which can be checked easily. For cases in which these conditions do not hold, at most log/sub 2/N-2 passes through the network are shown to be sufficient if a set of weaker conditions is satisfied. Techniques for routing data between processing elements through the faulty network are described. Extension of the results to general k-stage shuffle/exchange networks with k >

Fixed point models of loss networks

Abstract: In this paper we review a simple class of fixed point models for loss networks. We illustrate how these models can readily deal with heterogeneous call types and with simple dynamic routing strategies, and we outline some of the recent mathematical advances in the study of such models. We describe how fixed point models lead to a natural and tractable definition of the implied cost of carrying a call, and how this concept is related to issues of routing and capacity expansion in loss networks.

Markovian network processes: congestion-dependent routing and processing

Abstract: A Markovian network process describes the movement of discrete units among a set of nodes that process the units. There is considerable knowledge of such networks, often called queueing networks, in which the nodes operate independently and the routes of the units are independent. The focus of this study, in contrast, is on networks with dependent nodes and routings. Examples of dependencies are parallel processing across several nodes, blocking of transitions because of capacity constraints on nodes, alternate routing of units to avoid congestion, and accelerating or decelerating the processing rate at a node depending on downstream congestion. We introduce a general network process representing the numbers of units at the nodes and derive its equilibrium distribution. This distribution takes the form of a product of functions of vectors in which the arguments of the functions satisfy an interchangeability property. This new type of distribution may apply to other multi-variate processes as well. A basic idea in our approach is a linking of certain micro-level balance properties of the network routing to the processing rates at the nodes. The link is via “ routing-balance partitions” of nodes that are inherent in any network. A byproduct of this approach is a general characterization of blocking of transitions without the restriction that the process is reversible, which had been a standard assumption. We also give necessary and sufficient conditions under which a unit moving in the network sees a time average for the unmoved units (called the MUSTA property). Finally, we discuss when certain flows between nodes in an open network are Poisson processes.

The optimal control of heterogeneous queueing systems: a paradigm for load-sharing and routing

Abstract: The essence of the basic control decisions implicit in load-sharing and routing algorithms is captured in a simple model of heterogeneous queue control. The authors solve for the optimal control policy and investigate the performance of previously proposed policies in a tractable limit of this model. Using their understanding of this solvable limit, the authors propose heuristic policies for the general model. Simulation data for these policies suggest that they perform well over a wide range of system parameters. >

Hierarchical placement and floorplanning in BEAR

Abstract: Hierarchical placement and floorplanning algorithms for rectangular blocks are described and implemented as part of the BEAR building block layout system developed at the University of California at Berkeley. The algorithm combines the goal orientation of top-down approaches with the block orientation of bottom-up techniques. The result is a meet-in-the-middle strategy. It considers the mutual dependency between placement and routing explicitly by incorporating a novel method of hierarchical routing area estimation. If the layout includes flexible blocks, the placement result can be further optimized by resizing these blocks subject to constraints on their areas and aspect ratios. Placement and floorplanning are refined more and more (with possible topological change) as routing proceeds. Global routing is updated incrementally to eliminate the need for iterations between placement and routing, thus achieving a more uniform design flow. >

Optimum Design of Reliable IC Power Networks Having General Graph Topologies

Abstract: This paper deals with the problem of sizing integrated circuit power and ground distribution systems external to the logic modules constituting an integrated circuit. Several constraints associated with the reliability of the power and ground distribution systems are formulated. Algorithms are developed to determine the widths of the power and ground routes so that the area required by the routes is minimized subject to the constraints imposed. Run time results are included.

A quadrisection-based combined place and route scheme for standard cells

Abstract: A description is given of a placement technique based on hypergraph quadrisection The authors have developed a standard cell placement procedure based on recursively dividing the netlist into four parts, while minimizing the division cost They have combined two ideas for placement One is the extension of the min-cut bisection algorithm to handle quadrisection The second idea is the simultaneous calculation of min-cut quadrisection and hierarchical global routing The implementation details are discussed The results show the implementation to be competitive with simulated annealing >

Excellerator: custom CMOS leaf cell layout generator

Abstract: A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical design system. Transistor routing is provided by a novel, recursive version of the A-Star search procedure. This technique reduces the frequency and seriousness of routing blockages by finding near-optimal compromises between new connections and reroutes of previous connections. Routing occurs in two metal layers plus polysilicon and diffusion, and is easily extendable to any number of routing layers. Routing priority can be given to critical nodes. >