Showing papers on "Routing (electronic design automation) published in 1990"

Split delivery routing

Abstract: This article examines a relaxed version of the generic vehicle routing problem. In this version, a delivery to a demand point can be split between any number of vehicles. In spite of this relaxation the problem remains computationally hard. Since only small instances of the vehicle routing problem are known to be solved using exact methods, the vehicle route construction for this problem version is approached using heuristic rules. The main contribution of this article to the existing body of literature on vehicle routing issues in (a) is presenting a new vehicle routing problem amenable to practical applications, and (b) demonstrating the potential for cost savings over similar “traditional” vehicle routing when implementing the model and solutions presented here. The solution scheme allowing for split deliveries is compared with a solution in which no split deliveries are allowed. The comparison is conducted on six sets of 30 problems each for problems of size 75, 115, and 150 demand points (all together 540 problems). For very small demands (up to 10% of vehicle's capacity) no significant difference in solutions is evident for both solution schemes. For the other five problem sets for which point demand exceeds 10% of vehicle's capacity, very significant cost savings are realized when allowing split deliveries. The savings are significant both in the total distance and the number of vehicles required. The vehicles' routes constructed by our procedure tend to cover cohesive geographical zones and retain some properties of optimal solutions.

Clock routing for high-performance ICs

Abstract: Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed. >

Recent advances in VLSI layout

Abstract: The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

A predictive access-controll and routing system for integrated services telecommunication networks

Abstract: A predictive access-control and routing system for a telecommunications network operating in uncertain environments and capble of handling heterogeneous traffic. The system is a real-time, state-dependent network traffic control system in which the control strategy is a function of both real-time congestion levels and real-time traffic profiles. At specific time epochs, the system, using real-time measurements of source-destination arrival dates and trunk group link occupancies, generates predictions of all network trunk group occupancy levels for the next epoch as a function of routing and access control. It then minimizes a projected cost function, such as blocking, to generate a traffic control policy to be implemented during the next time interval.

Addressing, routing, and broadcasting in hexagonal mesh multiprocessors

Abstract: A family of six-regular graphs, called hexagonal meshes or H-meshes, is considered as a multiprocessor interconnection network. Processing nodes on the periphery of an H-mesh are first wrapped around to achieve regularity and homogeneity. The diameter of a wrapped H-mesh is shown to be of O(p/sup 1/2/), where p is the number of nodes in the H-mesh. An elegant, distributed routing scheme is developed for wrapped H-meshes so that each node in an H-mesh can compute shortest paths from itself to any other node with a straightforward algorithm of O(1) using the addresses of the source-destination pair only, i.e. independent of the network's size. This is in sharp contrast with those previously known algorithms that rely on using routing tables. Furthermore, the authors also develop an efficient point-to-point broadcasting algorithm for the H-meshes which is proved to be optimal in the number of required communication steps. The wrapped H-meshes are compared against some other existing multiprocessor interconnection networks, such as hypercubes, trees, and square meshes. The comparison reinforces the attractiveness of the H-mesh architecture. >

System and method for deferred processing of OCR scanned mail

Abstract: The invention is characterized as a data processing architecture and method for multi-stage processing of mail, using knowledge based techniques. The system includes OCR-scanning a multipart address field of a mail piece at a sending location, the address field including at least two portions, a first stage routing portion (destination city, state, country, zip code) and a second stage routing portion (destination street address, building floor, corporate addressee internal routing). At the sending location, the image of the entire address field is captured by an OCR head and stored in memory. A serial number is printed on the mail piece. The first routing portion is then converted into sorting signals to sort the mail piece to a truck at the sending location which is to be dispatched to the city, state and country indicated in the first stage routing portion. Then, while the mail piece is in transit by truck to the destination city, the image of the second stage routing portion is analyzed by a knowledge base processor to resolve street addresses, building floor, corporate addressee internal routing information and addressee name. The deferred execution of the analysis by the knowledge base processor is available because of the sporadic volume of mail pieces submitted to the sytem. While the mail piece is in transit on the truck, the knowledge processor completes its analysis and is able to transmit by electronic communications link to the destination location, the information that the mail piece is on its way and the second stage routing information needed to automatically sort and deliver the mail piece to its corporate addressee.

Serial interfacing for embedded-memory testing

Abstract: A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits for telecommunications. Even though the method uses serial access to the memory, a test pattern is applied every clock cycle because the memory itself shifts the test data. The method has been adapted to four common algorithms. In implementations of built-in self-test circuitry on several product chips, the area overhead was found to be acceptable. >

The Olympus synthesis system

Abstract: A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of supporting placement and routing tools, Olympus provides an interface to standard physical design tools. The system supports the synthesis of ASICs (application specific integrated circuits) from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips, and has been tested against benchmark circuits for high-level and logic synthesis. >

Adaptive fault-tolerant routing in hypercube multicomputers

Abstract: A connected hypercube with faulty links and/or nodes is called an injured hypercube. A distributed adaptive fault-tolerant routing scheme is proposed for an injured hypercube in which each node is required to know only the condition of its own links. Despite its simplicity, this scheme is shown to be capable of routing messages successfully in an injured n-dimensional hypercube as long as the number of faulty components is less than n. Moreover, it is proved that this scheme routes messages via shortest paths with a rather high probability, and the expected length of a resulting path is very close so that of a shortest path. Since the assumption that the number of faulty components is less than n in an n-dimensional hypercube might limit the usefulness of the above scheme, a routing scheme based on depth-first search which works in the presence of an arbitrary number of faulty components is introduced. Due to the insufficient information on faulty components, however, the paths chosen by this scheme may not always be the shortest. To guarantee all messages to be routed via shortest paths, the authors propose to equip every node with more information than that on its own links. The effects of this additional information on routing efficiency are analyzed, and the additional information to be kept at each node for the shortest path routing is determined. Several examples and remarks are given to illustrate the results. >

Depth-first search approach for fault-tolerant routing in hypercube multicomputers

Abstract: Using depth-first search, the authors develop and analyze the performance of a routing scheme for hypercube multicomputers in the presence of an arbitrary number of faulty components. They derive an exact expression for the probability of routing messages by way of optimal paths (of length equal to the Hamming distance between the corresponding pair of nodes) from the source node to an obstructed node. The obstructed node is defined as the first node encountered by the message that finds no optimal path to the destination node. It is noted that the probability of routing messages over an optimal path between any two nodes is a special case of the present results and can be obtained by replacing the obstructed node with the destination node. Numerical examples are given to illustrate the results, and they show that, in the presence of component failures, depth-first search routing can route a message to its destination by means of an optimal path with a very high probability. >

Simulation model generation from a physical data base of a combinatorial circuit

Abstract: A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root. As each tree is traversed, Boolean equations identifying the logical values at each node encountered are determined in accordance with a set of relationships pertinent to the standard circuit elements and a set of logic value assignment definitions. The resulting set of Boolean equations is used to construct the gate-level netlist that is incorporated into the simulation model of the macrocell.

New algorithms for the placement and routing of macro cells

Abstract: Novel algorithms are described for timing driven placement and routing of rectilinearly shaped macro cells. Algorithms are also presented for the implementation of simulated annealing, based on a theoretically derived statistical annealing schedule. A negative feedback scheme is described that optimizes the relative weighting between the primary objective term and the penalty function terms in the cost function. A placement refinement method has been developed for rectilinear cells which spaces the cells at a density which avoids the need for post-routing compaction. In addition, a detailed routing method has been developed which avoids the classically difficult problem of defining channels for detailed routing. The result for the ami33 benchmark circuit is better than the previously published results. >

Polychannel systems for mass digital communications

Abstract: A new type of distributed computer system looks toward the time when computers will be used by everyone everywhere.

On well-partial-order theory and its application to combinatorial problems of VLSI design

Abstract: We nonconstructively prove the existence of decision algorithms with low-degree polynomial running times for a number of well-studied graph layout, placement, and routing problems. Some were not previously known to be in p at all; others were only known to be in p by way of brute force or dynamic programming formulations with unboundedly high-degree polynomial running times. Our methods include the application of the recent Robertson-Seymour theorems on the well-partial-ordering of graphs under both the minor and immersion orders. We also briefly address the complexity of search versions of these problems.

Adaptive routing in a parallel computing system

Abstract: A multi-dimensional, multi-nodal routing mechanism is described for relaying information from node to node using a header consisting of route descriptor bits. Each node's receiver/transmitter pair changes states as the information is guided to the destination node. The message is propagated over several nodes simultaneously to traverse the nodes and reach the destination node quickly. When the final node is reached, all alternate communication routes are freed.

A gridless router for industrial design rules

Abstract: A point-to-point routing algorithm with three new features is presented. First, the router makes optimal use of oversized, rectangular contacts. Second, it allows different wire width on different layers, with the layers having complete freedom as to routing direction. These two features make the algorithm attractive for MOS layout applications. Finally, it is able to realize an all-angle routing and to accept all-angle obstacles, a feature interesting for hybrid and PCB routing. The router is gridless and guarantees a solution if one exists. Since it is based on computational geometry algorithms, it offers a low run-time complexity. The ideas have been implemented in a prototype version for 45 degrees routing. The results indicate that the router performs well, even on large designs. >

Segmented channel routing

Abstract: Routing channels in a field-programmable gate array contain predefined wiring segments of various lengths. These may be connected to the pins of the gates or joined end-to-end to form longer segments by programmable switches. A segmented channel routing problem is formulated, and polynomial time algorithms are given for certain special cases. The general problem is NP-complete, but it can be adequately solved in practice with reasonable CPU time by heuristics. The experiments show that a segmented channel can generally accommodate connections using only a few more tracks than a conventional channel would. >

Tailor: a layout system based on trapezoidal corner stitching

Abstract: A VLSI layout design system named Tailor is described. Tailor operates on hierarchical layouts containing 45 degrees multiple angles. It consists of a well-integrated set of tools, including a window-driven editor, an incremental design rule checker, a circuit extractor, a one-dimensional compactor, a channel-based global router, and a transistor size optimizer. All tools use the same user interface and operate directly on Tailor's trapezoidal corner stitched database. Tailor's database structure is well suited for all of the tools because all important database operations, such as point searching, neighbor searching, area searching, and shadow searching, function very efficiently. All the tools in Tailor, except transistor optimization and routing, work directly on the layout hierarchy, which provides even greater efficiency. >

Packet parallel interconnection network

Abstract: A packet parallel interconnection network for routing packets in parallel form comprises a three-dimensional space domain switch which interconnects a plurality of time domain switches in the form of multiple two level bus systems with separate data and control paths. The space domain switch comprises one control plane and a plurality of data switching planes such that the i th data switching plane routes the i th data slice of a packet. The control plane and the data switching planes comprise output buffered crosspoint switches. The control plane processes address information in the packets to be routed and broadcasts routing information to the data switching planes to control the routing of data slices by the data switching planes. It is a significant advantage of the time and space domain switches that decoupled control and data paths provide for overlapped control processing and data routing. The inventive interconnection network is especially useful for implementing a parallel processing system for processing database queries.

Constraint generation for routing analog circuits

Abstract: An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >

Floorplanning with pin assignment

Abstract: A hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for a Xerox general cell benchmark are reported. >

A unified approach to off-line permutation routing on parallel networks

Abstract: A unified framework for finding efficient permutation routes on parallel networks in an off-line setting is presented. If the underlying graph of a parallel network contains an appropriate “approximate” product structure then our method guarantees the existence of non-blocking near-optimal permutation routes. The routes in question can be determined in polynomial time. Furthermore, our results are extended to finding permutation routes among the remaining “live” nodes in a faulty network.

Distributed routing with on-line marginal delay estimation

Abstract: A procedure is presented for estimating online marginal packet delays through links with respect to link flows without making the standard assumptions (exponentially distributed packet lengths, Poisson arrival processes). This procedure is based on a technique known as perturbation analysis. No knowledge of network parameters (arrival rates, link capacities) is required. This is used in the context of a minimum delay distributed routing algorithm for real-time implementation. Experimental results are included to investigate the effect of the algorithm step-size and observation period parameters, demonstrate the adaptivity of the approach, and compare it to well-known analytical approximation. >

A new global router based on a flow model and linear assignment

Abstract: A novel heuristic for global routing in graphs is developed. Based on a flow model it can handle many nets simultaneously, thus reducing the net ordering problem. To demonstrate the validity of the method it was applied to standard cell design style. For this application the authors combined the flow model approach with linear assignment to achieve a hierarchical global routing scheme. This procedure is about six times faster than the old flat net by net global router, while producing denser layouts for the majority of testcases. Good quality was achieved in comparison with the TimberwolfSC version 5.4 global router. >

An analytical approach to floorplan design and optimization

Abstract: An analytical method for VLSI general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and all application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions, such as chip area, interconnection length, timing delays or any combinations of them, are permitted. Routing space is estimated by the global router. Experimental data are provided. >

Fast algorithms for bit-serial routing on a hypercube

Abstract: In this paper we describe anO(logN)-bit-step randomized algorithm for bit-serial message routing on a hypercube. The result is asymptotically optimal, and improves upon the best previously known algorithms by a logarithmic factor. The result also solves the problem of on-line circuit switching in anO(1)-dilated hypercube (i.e., the problem of establishing edge-disjoint paths between the nodes of the dilated hypercube for any one-to-one mapping).