Showing papers on "Routing (electronic design automation) published in 1992"

The active badge location system

Abstract: A novel system for the location of people in an office environment is described. Members of staff wear badges that transmit signals providing information about their location to a centralized location service, through a network of sensors. The paper also examines alternative location techniques, system design issues and applications, particularly relating to telephone call routing. Location systems raise concerns about the privacy of an individual and these issues are also addressed.

Radio frequency local area network

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

The Vehicle Routing Problem with Stochastic Travel Times

Abstract: This paper considers vehicle routing problems (VRPs) with stochastic service and travel times, in which vehicles incur a penalty proportional to the duration of their route in excess of a preset constant. Three mathematical programming models are presented: a chance constrained model, a three-index simple recourse model and a two-index recourse model. A general branch and cut algorithm for the three models is described. Computational results indicate that moderate size problems can be solved to optimality.

Wiring considerations in analog VLSI systems, with application to field-programmable networks

Abstract: This thesis develops a theoretical model for the wiring complexity of wide classes of systems, relating the degree of connectivity of a circuit to the dimensionality of its interconnect technology. This model is used to design an efficient, hierarchical interconnection network capable of accommodating large classes of circuits. Predesigned circuit elements can be incorporated into this hierarchy, permitting semi-customization for particular classes of systems (e.g., photoreceptors included on vision chips). A polynomial-time programming algorithm for embedding the desired circuit graph onto the prefabricated routing resources is presented, and is implemented as part of a general design tool for specifying, manipulating and comparing circuit netlists. This thesis presents a system intended to facilitate analog circuit design. At its core is a VLSI chip that is electrically configured in the field by selectively connecting predesigned elements to form a desired circuit, which is then tested electrically. The system may be considered a hardware accelerator for simulation, and its large capacity permits testing system ideas, which is impractical using current means. A fast-turnaround simulator permitting rapid conception and evaluation of circuit ideas is an invaluable aid to developing an understanding of system design in a VLSI context. We have constructed systems using both reconfigurable interconnection switches and laser-programmed interconnect. Prototypes capable of synthesizing circuits consisting of over 1000 transistors have been constructed. The flexibility of the system has been demonstrated, and data from parametric tests have proven the validity of the approach. Finally, this thesis presents several new circuits that have become key components in many analog VLSI systems. Fast, dense and provably safe one-phase latches and hierarchical arbiters are presented, as are a low-noise analog switch, an isotropic novelty filter, a dense, active high-resistance element, and a subthreshold differential amplifier with a large linear input range.

Large capacity, random access, multi-source recorder player

Abstract: An audio/video recorder system receives a plurality of transmission signals each containing program information and simultaneously stores the received transmission signals. The system can be controlled by user input to allow for automatic recording of selected programs simultaneously input from multiple sources, reconfiguration of stored programs, and routing of stored programs to selected outputs.

Subscriber call routing processing system

Abstract: A method is described for routing calls outside of a carriers network based on characteristics of the call, the attributes of the caller, the status of subscriber-provided resource, and the status of network telephone provided facilities. Information about the call and the caller's identification is sent from the public switched telephone network to a subscriber call routing processor. The carrier is directed by the routing processor to route the call to the subscriber's resource best able to handle the call. Information about the call and the business relationship the caller has with the subscriber is used by the routing processor to determine which type of resource is needed to handle the call. The routing processor then chooses the particular resource of that type to which the call is to be routed based on the current status of the resource, the status of the network-provided facilities, and the criteria established by the subscriber for selecting between alternative resources. Resource types may include any PSTN terminations, including automatic call distributors, audio response units, modems, and individual stations. The routing processor may also send information to the carrier to be delivered to the subscriber resource to assist in handling the call.

Provably good performance-driven global routing

Abstract: The authors propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. The authors first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, they give an algorithm which simultaneously minimizes both routing cost and the longest interconnection path, so that both are bounded by small constant factors away from optimal. They also show that geometry helps in routing: in the Manhattan plane, the total wire length for Steiner routing improves to 3/2*(1+(1/ epsilon )) times the optimal Steiner tree cost, while in the Euclidean plane, the total cost is further reduced to (2/ square root 3)*(1+(1/ epsilon )) times optimal. The method generalizes to the case where varying wire length bounds are prescribed for different source-sink paths. Extensive simulations confirm that this approach works well. >

Routing with polynomial communication-space trade-off

Abstract: This paper presents a family of memory-balanced routing schemes that use relatively short paths while storing relatively little routing information. The quality of the routes provided by a scheme is measured in terms of their stretch, namely, the maximum ratio between the length of a route connecting some pair of processors and their distance. The hierarchical schemes$\mathcal{H}_k $ (for every integer $k\geqq 1$) presented in this paper guarantee a stretch factor of $O( k^2 )$ on the length of the routes and require storing at most $O( k \cdot n^{1/k} \cdot \log n\log D )$ bits of routing information per vertex in an n-processor network with diameter D. The schemes are name independent and applicable to general networks with arbitrary edge weights. This improves on previous designs whose stretch bound was exponential in k.The proposed schemes are based on a new efficient solution to a certain graph-theoretic problem concerning sparse graph covers. The new cover technique has already found several other a...

Method for optimizing a network having virtual circuit routing over virtual paths

Abstract: Virtual circuits are routed and grouped into virtual paths during an interactive topology design process. Virtual circuits are assigned to virtual paths that provide minimum cost to each pass through a topology design. Virtual paths are dispersed into subgroups that minimize bandwidth consumption and maximize routing flexibility. This topology optimization process is constrained to minimize use of network resources.

Facsimile message processing and routing system

Abstract: In this invention, a processor connected to a communication switching system i) intercepts or receives each facsimile message destined for a receiving party, ii) analyzes at least a portion of each message to collect, in addition to the called number, other routing information from the transmitted message, iii) converts the message to a different format, if necessary and iv) delivers that message to at least one of a plurality of other destination facsimile terminals based on a) the routing information gathered from the message and b) pre-arranged routing information stored in the processor and provided by the receiving party.

A fault-tolerant communication scheme for hypercube computers

Abstract: A fault-tolerant communication scheme that facilitates near-optimal routing and broadcasting in hypercube computers subject to node failures is described. The concept of an unsafe node is introduced to identify fault-free nodes that may cause communication difficulties. It is shown that by only using 'feasible' paths that try to avoid unsafe nodes, routing and broadcasting can be substantially simplified. A computationally efficient routing algorithm that uses local information is presented. It can route a message via a path of length no greater than p+2, where p is the minimum distance from the source to the destination, provided that not all nonfaulty nodes in the hypercube are unsafe. Broadcasting can be achieved under the same fault conditions with only one more time unit than the fault-free case. The problems posed by deadlock in faulty hypercubes are discussed, and deadlock-free implementations of the proposed communication schemes are presented. >

Field-Programmable Gate Arrays

Abstract: Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.

An O(log N) deterministic packet-routing scheme

Abstract: A deterministic O(log N)-time algorithm for the problem of routing an aribitrary permutation on an N-processor bounded-degree network with bounded buffers is presented.Unlike all previous deterministic solutions to this problem, our routing scheme does not reduce the routing problem to sorting and does not use the sorting network of Ajtai, et al. [1]. Consequently, the constant in the run time of our routing scheme is substantially smaller, and the network topology is significantly simpler.

An efficient logic emulation system

Abstract: The Realizer, a system which automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. The interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds or thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 XC3090 FPGAs for logic. A 32-b CPU datapath has been automatically realized and operated at speed, and demonstrates very good FPGA utilization. >

Exact analysis of hot-potato routing

Abstract: The authors consider a form of packet routing known as hot potato routing or deflection routing. Its striking feature is that there are no buffers at intermediate nodes. Thus packets are always moving (possibly in the 'wrong' direction), giving rise to the term 'hot potato'. They give a simple deterministic algorithm that on a n*n torus will route a random instance in 2n+O(log n) steps with high probability. They add random delays to this algorithm so that it solves the permutation routing problem on the torus in 9n steps with high probability, on every instance. On a hypercube with N=2/sup n/ nodes, they give a simple deterministic algorithm that will route a random instance in O(n) steps with high probability. Various other results are discussed. >

A New Branching Strategy for Time Constrained Routing Problems with Application to Backhauling

Abstract: In this paper, we explore a new branching strategy for branch-and-bound approaches based on column generation for the vehicle routing problems with time windows. This strategy involves branching on resource variables (time or capacity) rather than on network flow variables. We also examine criteria for selecting network nodes for branching. To test the effectiveness of the branching strategy, we conduct computational experiments on time window constrained vehicle routing problems where backhauling is permitted only after all the shipments to clients have been made. The branching method proved very effective. In cases where time was the more binding constraint, time-based branching succeeded in decreasing the number of nodes explored by two thirds and the total computation time by more than half when compared to flow-based branching. The computational results also show that the overall algorithm was successful in optimally solving problems with up to 100 customers. It produced an average cost decrease of almost 7% when backhauling was permitted as compared to the cost involved when the client and the distributor routes were distinct.

Deflection routing in hypercube networks

Abstract: An approximate analysis of the transient and steady state behavior of deflection routing in hypercube networks is presented, under a uniform traffic model. In deflection routing congestion causes packets admitted to the network to be temporarily misrouted rather than buffered or dropped. The approximations show that deflection routing performs remarkably well in hypercube networks, for small as well as large networks and for the whole range from light to heavy load. Simulations suggest that the approximations are quite accurate. >

Iterative and adaptive slack allocation for performance-driven layout and FPGA routing

Abstract: The authors gives a generalization, called the limit-bumping algorithm (LBA), of a procedure of H. Youssef et al. (1990) that transforms initial connection delays into upper limits on delay suitable for performance-driven layout. LBA is a simple way to distribute slacks using arbitrary allocation functions. It is shown that lower and upper bounds on connection delays can be used in the computation of upper limits for initial layout and for layout improvement. The methods have been integrated into a delay-sensitive router for field programmable gate arrays (FPGAs). In 22 standard benchmark designs, feasible system clock periods were reduced in every case by an average of 14% and as much as 32%. >

Internetworking apparatus for connecting plural network systems and communication network system composed of plural network systems mutually connected

Abstract: An internetworking apparatus which handles a scale of a network flexibly without degrading high speed operation. A router manager and a plurality of routing accelerator modules for performing routing are connected to one another through a high speed bus, and a plurality of communication ports are connected to the respective routing accelerators independently of one another. The plurality of routing accelerators can perform the routing for reception data packet at high speed. If more routing accelerators are provided, the disposal to the networks having a small scale to a large scale can be readily realized.

Crosspoint matrix switching element for a packet switch

Abstract: A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 13401,1, 13402,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 11151, 11152, . . . , 1115K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (2781, 2782, . . . , 278N) of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs.

Routing in virtual path based ATM networks

Abstract: The issue of routing requests for virtual circuits in a virtual path (VP) based asynchronous transfer mode (ATM) network is addressed. It is supposed that the VPs are partitioned in a manner such that all the virtual circuits (VCs) making use of any given VP have the same traffic characteristics and quality of service demands. A virtual circuit request can be accepted in the network only if the specified loss and delay bounds can be guaranteed for the cells belonging to it. After suitable simplifying assumptions about the operation of the network are made, simple admission rules for virtual circuit requests are proposed. Routing policies are then proposed that try to minimize the fraction of virtual circuit requests denied. Simulations are carried out to evaluate the proposed routing policies. >

On well-partial-order theory and its application to combinatorial problems of VLSI design

Abstract: The existence of decision algorithms with low-degree polynomial running times for a number of well-studied graph layout, placement, and routing problems is nonconstructively proved. Some were not previously known to be in $\mathcal{P}$ at all; others were only known to be in $\mathcal{P}$ by way of brute force or dynamic programming formulations with unboundedly high-degree polynomial running times. The methods applied include the recent Robertson–Seymour theorems on the well-partial-ordering of graphs under both the minor and immersion orders. The complexity of search versions of these problems is also briefly addressed.

RITUAL: a performance driven placement algorithm

Abstract: An algorithm for obtaining a placement of large scale cell-based ICs subject to performance constraints is described. The problem is formulated as a constrained programming problem and is solved in two phases: continuous and discrete. Constraints are placed on total path delays including cell and interconnect delays, and the behavior of all the paths is captured. Mathematical techniques and heuristics based on Lagrangian relaxation are used to find an approximate solution to the constrained problem. The algorithm yields good results, as shown on a set of real examples. On the average, between 8% and 30% improvement in the interconnect delay of these examples is obtained with little or no impact on chip area after routing by modifying the placement alone. >

A tabu search heuristic for the vehicle routing problem with time windows

Abstract: This paper describes a tabu search heuristic for the Vehicle Routing Problem with Time Windows (VRPTW). The tabu search incorporates an exchange heuristic which is specifically designed for problems with time windows. Computational results on the standard set of problems of Solomon are included at the end of the paper.

Least cost routing method according to information transfer capability of customer premises equipment

Abstract: ISDN subscriber line interface circuits of a switching system serve customer premises equipment of different information transfer capabilities. Least cost routing data and corresponding digit conversion data are stored in a memory, with the routing data indicating least cost outgoing routes through an ISDN network. These data are retrieved from the memory according to the called party number and information transfer capability field of a call setup message received from a calling party. The called party number is then converted according to the retrieved digit conversion data, and an ISDN trunk circuit is selected according to the retrieved least cost routing data. A connection is established between the originating ISDN SLIC and the selected ISDN trunk circuit, and the converted called party number is transmitted through a signaling channel to the ISDN network.

A simulated annealing technique approach to the vehicle routing problem in the case of stochastic demand

Abstract: Research work dealing with the vehicle routing problem has not paid adequate attention to the cases where the demand for services at certain nodes is a random variable. This paper develops an approach to the vehicle routing problem for the case of stochastic demand. The approach is based on the simulated annealing technique. It is illustrated with a numerical example.

A yield improvement technique for IC layout using local design rules

Abstract: The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples. >