Showing papers on "Routing (electronic design automation) published in 1993"

A new theory of deadlock-free adaptive routing in wormhole networks

Abstract: The theoretical background for the design of deadlock-free adaptive routing algorithms for wormhole networks is developed. The author proposes some basic definitions and two theorems. These create the conditions to verify that an adaptive algorithm is deadlock-free, even when there are cycles in the channel dependency graph. Two design methodologies are also proposed. The first supplies algorithms with a high degree of freedom, without increasing the number of physical channels. The second methodology is intended for the design of fault-tolerant algorithms. Some examples are given to show the application of the methodologies. Simulations show the performance improvement that can be achieved by designing the routing algorithms with the new theory. >

Fast routing table lookup using CAMs

Abstract: The authors investigate fast routing table lookup techniques, where the table is composed of hierarchical addresses such as those found in a national telephone network. The hierarchical addresses provide important benefits in large networks, but existing fast routing table lookup techniques, based on hardware such as content addressable memory (CAM), work only with flat addresses. Several fast routing table lookup solutions for hierarchical address based on binary and ternary CAMs are presented, and their advantages and drawbacks are analyzed. >

Architecture of field-programmable gate arrays

Abstract: A survey of field-programmable gate array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their volatility, size parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classification of logic blocks based on their granularity is proposed, and several logic blocks used in commercially available FPGAs are described. A brief review of recent results on the effect of logic block granularity on logic density and performance of an FPGA is then presented. Several commercial routing architectures are described in the context of a general routing architecture model. Finally, recent results on the tradeoff between the flexibility of an FPGA routing architecture, its routability, and its density are reviewed. >

Distance approximations for routing manual pickers in a warehouse

Abstract: This paper evaluates and compares strategies for routing a manual picker through a simple warehouse. It expands on previous work, in which optimization algorithms were developed, by deriving equations which relate route length to warehouse attributes. Several rules of thumb are derived for selection of order picking strategies and optimization of warehouse shape.

Loop-free routing using diffusing computations

Abstract: A family of distributed algorithms for the dynamic computation of the shortest paths in a computer network or internet is presented, validated, and analyzed. According to these algorithms, each node maintains a vector with its distance to every other node. Update messages from a node are sent only to its neighbors; each such message contains a distance vector of one or more entries, and each entry specifies the length of the selected path to a network destination, as well as an indication of whether the entry constitutes an update, a query, or a reply to a previous query. The new algorithms treat the problem of distributed shortest-path routing as one of diffusing computations, which was first proposed by Dijkstra and Scholten (1980). They improve on a number of algorithms introduced previously. The new algorithms are shown to converge in finite time after an arbitrary sequence of link cost or topological changes, to be loop-free at every instant, and to outperform all other loop-free routing algorithms previously proposed from the standpoint of the combined temporal, message, and storage complexities. >

Design for assembly

Abstract: The development and use of a software program that not only predicts a board's cost but also provides indices of its manufacturability, called PCB Design for Assembly (PCB/DFA), are described. The software is intended to reduce design cycle time and manufacturing cost. Well before placement and routing, it quickly generates 'on paper' alternative board designs that would be economical to manufacture. >

An Architecture for IP Address Allocation with CIDR

Abstract: have no defined hierarchical relationship, administrators would not be able to assign IP addresses within the domains out of some common prefix for the purpose of data abstraction The result would be flat inter-domain routing; all routing domains would need explicit knowledge of all other routing domains that they route to This can work well in small and medium sized internets, up to a size somewhat larger than the current Internet However, this does not scale to very large internets For example, we expect growth in the future to an Internet which has tens or hundreds of thousands of routing domains in North America alone This requires a greater degree of the reachability information abstraction beyond that which can be achieved at the `routing domain' level In the Internet, however, it should be possible to exploit the existing hierarchical routing structure interconnections, as discussed in Section 5 Thus, there is the opportunity for a group of routing domains each to be assigned an address prefix from a shorter prefix assigned to another routing domain whose function is to interconnect the group of routing domains Each member of the group of routing domains now `owns' its (somewhat longer) prefix, from which it assigns its addresses The most straightforward case of this occurs when there is a set of routing domains which are all attached only to a single service provider domain (eg regional network), and which use that provider for all external (inter-domain) traffic A small prefix may be assigned to the provider, which then assigns slightly longer prefixes (based on the provider's prefix) to each of the routing domains that it interconnects This allows the provider, when informing other routing domains of the addresses that it can reach, to abbreviate the reachability information for a large number of routing domains as a single prefix This approach therefore can allow a great deal of hierarchical abbreviation of routing information, and thereby can

Hierarchically connectable configurable cellular array

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Method for routing items within a computer system

Abstract: A method and apparatus are provided for routing information with a pointer-based computer such as a pen-based computer. The routing actions may be faxing, printing, mailing (electronically), and beaming (by infrared light). The routed information may be document or other item produced by or associated with a particular application running on the computer. Routing actions that send items out of the computer system preferably are processed according to the following steps. First one or more menus or windows associated with the application of the document being routed are displayed on a display screen of the computer. At least one of these menus or windows contains a list of routing actions available to the application. The user selects one of these routing actions and, in some cases, provides additional information pertaining to the destination, format, etc. of the document being routed. Then the document or item being routed is transferred to an out box which resides, at least in part, in the memory of the computer system. The out box is communication with a plurality of ports such as a modem, an IR beam transceiver, etc. From the out box, the item is routed out of the computer system and through one of the ports and the process is concluded.

An exact zero-skew clock routing algorithm

Abstract: An exact zero-skew clock routing algorithm using the Elmore delay model is presented. The results have been verified with accurate waveform simulation. The authors first review a linear time delay computation method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multistaged clock trees, and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed. >

A Clustering-Based Optimization Algorithm in Zero-Skew Routings

Abstract: A zero-skew routing algorithm with clustering and improvement methods is proposed. This algorithm generates a zero-skew routing in O(n log n) time for n pins, and it is proven that the order of the total wire length is best possible. Our algorithm achieves 20% reduction of the total wire length on benchmark data compared with the best known algorithm.

Performance-Driven Interconnect Design Based on Distributed RC Delay Model

Abstract: In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or near-optimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for high-performance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm.

System and method for routing data and communications

Abstract: A system (10) for routing data and communications to one of a plurality of remote sites (14a and 14b) to promote reciprocal interaction among the remote sites. The system includes a central processing unit (20) and storage devices (22, 24 and 26) to store a first set of data identifying a plurality of remote sites and a second set of data identifying the frequency at which each of the remote sites communicates with the system. The system further includes means (22) for analyzing the second data to select a particular remote site to receive a particular communication. The system also contemplates a method of routing data and communications including the steps of storing routing data for identifying a plurality of remote sites and the frequency at which each of the remote sites communicates with a central processor, receiving a communication at the central processor, analyzing the routing data to select a particular remote site, and forwarding the communication to the selected remote site.

Minimum crosstalk channel routing

Abstract: As technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction of crosstalk between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded channel routing problem with the objective of satisfying crosstalk constraints for the nets. We proposed a new approach to the problem which utilizes existing channel routing algorithms and improves upon the routing results by permuting the routing tracks. The permutation problem is proven to be NP-complete. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The new algorithm is tested on three large benchmark circuits as well as many randomly generated circuits. The experimental results are very promising.

Fault-tolerant wormhole routing in meshes

Abstract: It is shown how to modify the routing algorithms produced by the turn model to encompass dynamic faults The authors describe how to modify the negative-first routing algorithm, which the turn model produces for n-dimensional meshes without virtual channels, to make it one-fault tolerant Simulations of the one-fault-tolerant routing algorithms in a two-dimensional mesh indicate that misrouting increases communication latencies significantly at high throughputs The conclusion is that misrouting should be used only for increasing the degree of fault tolerance, never for just increasing adaptiveness Finally, the authors describe how to modify the negative-first routing algorithm to make it (n-1)-fault tolerant for n-dimensional meshes

Developing conflict-free routes for automated guided vehicles

Abstract: Automated guided vehicles AGVs are a highly sophisticated and increasingly popular type of material handling device in flexible manufacturing systems. This paper details solution methodologies for the static routing problem in which demand assignment of the AGVs are known; the focus is to obtain an implementable solution within a reasonable amount of computer time. The objective is to minimize the makespan, while routing AGVs on a bidirectional network in a conflict-free manner. This problem is solved via column generation. The master problem in this column generation procedure has the makespan and vehicle interference constraints. Columns in the master problem are routes iteratively generated for each AGV. The subproblem is a constrained shortest path problem with time-dependent costs on the edges. An improvement procedure is developed to better the solution obtained at the end of the master-subproblem interactions. Several methods of iterating between the master and subproblem are experimented with in-depth computational experiments. Our empirical results indicate that the procedure as a whole usually generates solutions that are within a few percent of a proposed bound, within reasonable computer time.

Timing driven method for laying out a user's circuit onto a programmable integrated circuit device

Abstract: The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.

An integrated multicomponent synthesis environment for MCMs

Abstract: The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis support all the way from the behavioral level to MCM placement and routing, three levels of simulation support including behavioral, register, and switch levels, and tools for automated test-bench compilation and design validation for all synthesized designs. Three tutorial examples illustrate MSS algorithms and results. The primary example is the Find, which performs a bubble sort followed by binary search. It is used as the running example because it is small. Such small specifications, however, do not require MCMs. Two larger examples, the Move Machine and the Viper Microprocessor, are used to illustrate the results. >

Integrated approach to vehicle routing and congestion prediction for real-time driver guidance

Abstract: The generation and dissemination of driver guidance that can be used for real-time diversion of traffic are expected to be implemented through the use of real-time traveler information systems. To implement these functions, a system structure consisting of a surveillance module, a congestion prediction module, and a control and routing (CAR) module is proposed, with the focus on the approaches that may be used for congestion prediction and the strategies that may form the basis for routing. It is argued that a congestion prediction capability is critical for the effectiveness of an on-line traveler information system. Such a capability is required to accurately forecast traffic conditions that may exist in the near future. The use of a dynamic traffic assignment model for congestion prediction is suggested. Such a model consists of dynamic driver behavior and network performance modules as well as origin-destination updating capability. Alternatively, statistical time-series methods may be necessary to generate predictions of future traffic conditions. The advantages and difficulties of adopting either approach are discussed. The predicted congestion information is passed to the CAR module to develop diversion strategies to alleviate both recurring and nonrecurring congestion. The role of routing strategies and update frequency in determining guidance effectiveness is discussed.

SURF: rubber-band routing system for multichip modules

Abstract: Current PCB (printed circuit board)-based routing tools cannot meet the performance and cost constraints presented by today's packaging technologies, including thin-film multichip modules. The authors describe SURF, a routing system designed specifically to meet these challenges. The strength of the SURF system comes from its extremely flexible rubber-band data representation. The rubber-band model is an ideal framework for performance-driven and cost-driven routing and naturally supports rectilinear, octilinear, and all-angle wiring patterns: one-and-a-half-layer routing; even wiring distribution; and powerful manual editing. The integrated spoke-based design-rule-checking/enforcement mechanism supports an incremental design style. As objects are moved or wires are resized, the wires are adjusted incrementally so that they maintain the same wiring topology. By working in the topological domain instead of the geometrical one, the designer can focus on higher-level design issues while the tool handles the precise geometrical details. >

Method and system for maintaining routing between mobile workstations and selected network workstation using routing table within each router device in the network

Abstract: A method and system for maintaining a routing path between a selected workstation within a multisegment local area network and a mobile workstation wherein individual segments within the multisegment local area network are interconnected by a router device and wherein selected segments within the multisegment local area network include radio frequency transceivers adapted to provide a wireless communications link with mobile workstations. Each time communication is established between a mobile workstation and a selected workstation within the multisegment local area network via a radio frequency transceiver a routing table entry is established which identifies a segment location for the mobile workstation within a routing table associated with each router device within the multisegment local area network. A routing table entry is also established which identifies a segment location for the selected workstation within the routing table associated within each router device within the multisegment local area network in response to each attempt at establishment of communication between the selected workstation and the mobile workstation. Thereafter, all routing table entries which identify the segment location for a mobile workstation are automatically deleted in response to a termination of communications between the mobile workstation and the radio frequency transceiver. Routing path determination for communications between a mobile workstation and any workstation within the multisegment local area network may then be determined by reference to a routing table associated with each router device within a multisegment local area network without requiring the maintenance of routing path information at each workstation within the multisegment local area network.

Fidelity and near-optimality of Elmore-based routing constructions

Abstract: We address the efficient construction of interconnection trees with near-optimal delays. We study the accuracy and fidelity of easily-computed delay models with respect to detailed simulation (e.g., SPICE-computed delays). We show that Elmore delay minimization (W.C. Elmore, 1948) is a high-fidelity interconnect objective for IC interconnect technologies, and propose a greedy low delay tree (LDT) heuristic which for any monotone delay function can efficiently minimize maximum delay. For comparison, we also generate optimal routing trees (ORTs) with respect to Elmore delay, using branch-and-bound search. Experimental results show that the LDT heuristic approximates ORTs very accurately: for nets with up to seven pins, LDT trees have a maximum sink delay within 2.3% of optimum on average. Moreover, compared with minimum spanning tree constructions, the LDT achieves average reductions in delay of up to 35% depending on the net size. >

Performance-Driven Steiner Tree Algorithms for Global Routing

Abstract: This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms Experiment results are given to demonstrate the effectiveness of the two algorithms

Multicomputer memory access architecture

Abstract: A multicomputer is shown made up of a crossbar network to which are connected processing nodes and I/O interface nodes. The processing nodes include crossbar interface circuits that provide routing signals in local registers so that a local processor can access memory in remote processing nodes. The crossbars include circuits to establish communication paths through the crossbar networks in response to the routing signals, so that a local processor has direct access to remote memory, which is mapped into local address space. The routing signal can have a broadcast mode and can establish priority for the signal. Under some circumstances the crossbar circuit can choose between alternative paths through a crossbar. Arbitrary sized and shaped networks of crossbars can be readily implemented, and the direct memory burst transactions allow very high speed performance.

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization

Abstract: Recognizing that routing constraints and process variations make non-zero skew inevitable, this paper describes a novel methodology for constructing reliable low-skew clock trees. The algorithm efficiently calculates clock-tree delay sensitivities to achieve a target delay and a target skew. Moreover, the sensitivities also show that wires should be widened as opposed to lengthened to reduce skew since the former improves reliability while the latter reduces it. This paper introduces the concept of designing reliable clock nets with process-insensitive skew.

High-Performance Routing Trees with Identified Critical Sinks

Abstract: We present two critical-sink routing tree (CSRT) constructions which exploit critical-path information that becomes available during timing-driven layout. Our CS-Steiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower critical-sink delays compared with existing performance-driven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69% over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.

Performance evaluation of multipoint routing algorithms

Abstract: The problem of developing efficient multipoint routing algorithms for asynchronous transfer mode (ATM) networks is considered Emphasis is placed on practical algorithms that have efficient distributed implementation In particular, the weighted greedy algorithm (WGA) is investigated This algorithm is of particular interest since one version can be implemented as a simple extension of point-to-point routing and since a straightforward distributed implementation is possible The performance of the WGA is studied by means of computer simulations and compared to that of a theoretically good algorithm Experiments are conducted under realistic conditions involving different connection types, including point-to-point and dynamic multipoint connections Performance is evaluated in terms of an algorithm's load carrying potential The goal is to find algorithms that maximize the load carrying ability of a network >

Global combine on mesh architectures with wormhole routing

Abstract: Several algorithms are discussed for implementing global combine (summation) on distributed memory computers using a two-dimensional mesh interconnect with wormhole routing. These include algorithms that are asymptotically optimal for short vectors (O(log(p)) for p processing nodes) and for long vectors (O(n) for n data elements per node), as well as hybrid algorithms that are superior for intermediate n. Performance models are developed that include the effects of link conflicts and other characteristics of the underlying communication system. The models are validated using experimental data from the Intel Touchstone DELTA computer. Each of the combine algorithms is shown to be superior under some circumstances. >

A dynamic routing control based on a genetic algorithm

Abstract: It is demonstrated that dynamic routing control based on a genetic algorithm can provide flexible real-time management of the dynamic traffic changes in broadband networks. A string structure is proposed, each of whose elements represents paths between each pair of origin and destination terminal nodes, together with a new technique using the past solutions as the initial data for new searches. These techniques dramatically improve the efficiency and convergence speed of the genetic algorithm. Computer simulations show that the genetic algorithm using the proposed techniques can generate the exact solution of path arrangement and can find a routing arrangement that keeps the traffic loss-rate below a target value, even after changes in traffic. >