Showing papers on "Routing (electronic design automation) published in 1995"

Routing and wavelength assignment in all-optical networks

Abstract: Considers routing connections in a reconfigurable optical network using WDM. Each connection between a pair of nodes in the network is assigned a path through the network and a wavelength on that path, such that connections whose paths share a common link in the network are assigned different wavelengths. The authors derive an upper bound on the carried traffic of connections (or equivalently, a lower bound on the blocking probability) for any routing and wavelength assignment (RWA) algorithm in such a network. The bound scales with the number of wavelengths and is achieved asymptotically (when a large number of wavelengths is available) by a fixed RWA algorithm. The bound can be used as a metric against which the performance of different RWA algorithms can be compared for networks of moderate size. The authors illustrate this by comparing the performance of a simple shortest-path RWA (SP-RWA) algorithm via simulation relative to the bound. They also derive a similar bound for optical networks using dynamic wavelength converters, which are equivalent to circuit-switched telephone networks, and compare the two cases. Finally, they quantify the amount of wavelength reuse achievable in large networks using the SP-RWA via simulation as a function of the number of wavelengths, number of edges, and number of nodes for randomly constructed networks as well as de Bruijn networks. They also quantify the difference in wavelength reuse between two different optical node architectures. >

The General Pickup and Delivery Problem

Abstract: In pickup and delivery problems vehicles have to transport loads from origins to destinations without transshipment at intermediate locations. In this paper, we discuss several characteristics that distinguish them from standard vehicle routing problems and present a survey of the problem types and solution methods found in the literature.

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

Abstract: Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.

A comparison of classifiers and document representations for the routing problem

Abstract: In this paper, we compare learning techniques based on statistical classification to traditional methods of relevance feedback for the document routing problem. We consider three classification techniques which have decision rules that are derived via explicit error minimization: linear discriminant analysis, logistic regression, and neural networks. We demonstrate that the classifiers perform 1015% better than relevance feedback via Rocchio expansion for the TREC-2 and TREC-3 routing tasks. Error minimization is difficult in high-dimensional feature spaces because the convergence process is slow and the models are prone to overfitting. We use two different strategies, latent semantic indexing and optimal term selection, to reduce the number of features. Our results indicate that features based on latent semantic indexing are more effective for techniques such as linear discriminant analysis and logistic regression, which have no way to protect against overfitting. Neural networks perform equally well with either set of features and can take advantage of the additional information available when both feature sets are used as input.

A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks

Abstract: Deadlock avoidance is a key issue in wormhole networks. A first approach by W.J. Dally and C.L. Seitz (1987) consists of removing the cyclic dependencies between channels. Many deterministic and adaptive routing algorithms have been proposed based on that approach. Although the absence of cyclic dependencies is a necessary and sufficient condition for deadlock-free deterministic routing, it is only a sufficient condition for deadlock-free adaptive routing. A more powerful approach by J. Duato (1991) only requires the absence of cyclic dependencies on a connected channel subset. The remaining channels can be used in almost any way. In this paper, we show that the previously mentioned approach is also a sufficient condition. Moreover, we propose a necessary and sufficient condition for deadlock-free adaptive routing. This condition is the key for the design of fully adaptive routing algorithms with minimum restrictions, An example shows the application of the new theory. >

Arc Routing Problems, Part I: The Chinese Postman Problem

Abstract: Arc routing problems arise in several areas of distribution management and have long been the object of study by mathematicians and operations researchers. In the first of a two-part survey, the Chinese postman problem CPP is considered. The main algorithmic results for the CPP are reviewed in five main sections: the undirected CPP, the directed CPP, the windy postman problem, the mixed CPP, and the hierarchical CPP.

Fault-tolerant wormhole routing algorithms for mesh networks

Abstract: We present simple methods to enhance the current minimal wormhole routing algorithms developed for high radix, low dimensional mesh networks for fault tolerant routing. We consider arbitrarily located faulty blocks and assume only local knowledge of faults. Messages are routed minimally when not blocked by faults and this constraint is relaxed to route around faults. The key concept we use is a fault ring consisting of fault free nodes and links can be formed around each fault region. Our fault tolerant techniques use these fault rings to route messages around fault regions. We show that, using just one extra virtual channel per physical channel, the well known e cube algorithm can be used to provide deadlock free routing in networks with nonoverlapping fault rings; there is no restriction on the number of faults. For the more complex faults with overlapping fault rings, four virtual channels are used. We also prove that at most four additional virtual channels are sufficient to make fully adaptive algorithms tolerant to multiple faulty blocks in n dimensional meshes. All these algorithms are deadlock and livelock free. Further, we present simulation results for the e cube and a fully adaptive algorithm fortified with our fault tolerant routing techniques and show that good performance may be obtained with as many as 10% links faulty. >

Stochastic and dynamic networks and routing

Abstract: Publisher Summary This chapter discusses stochastic and dynamic networks and routing. The chapter discusses priori optimization in routing, shortest paths, traveling salesman-type problems and vehicle routing. These problems arise when decisions must be made before random outcomes (typically customer demands) are known. The chapter covers dynamic models of problems arising in transportation and logistics, and includes a discussion of important modeling issues, as well as a summary of dynamic models for a number of key problem areas. Dynamic networks provide an important foundation for addressing many problems in logistics planning. Algorithms that have been specialized for dynamic networks are presented. The results for solving infinite networks, including both exact results for stationary infinite networks, and model truncation techniques are briefly discussed. The chapter presents basic results and concepts from the field of stochastic programming, oriented toward their application to network problems. This discussion provides a general framework for formulating and solving stochastic, dynamic network problems. That framework is used to present two stochastic programming models.

A Location Based Heuristic for General Routing Problems

Abstract: We present a general framework for modeling routing problems based on formulating them as a traditional location problem called the capacitated concentrator location problem. We apply this framework to two classical routing problems: the capacitated vehicle routing problem and the inventory routing problem. In the former case, the heuristic is proven to be asymptotically optimal for any distribution of customer demands and locations. Computational experiments show that the heuristic performs well for both problems and, in most cases, outperforms all published heuristics on a set of standard test problems.

Architecture and interconnect scheme for programmable logic circuits

Abstract: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

CAD and simulation system for targeting IC designs to multiple fabrication processes

Abstract: Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

Collective communication in wormhole-routed massively parallel computers

Abstract: Most MPC networks use wormhole routing to reduce the effect of path length on communication time. Researchers have exploited this by designing ingenious algorithms to speed collective communication. Many projects have addressed the design of efficient collective communication algorithms for wormhole-routed systems. By exploiting the relative distance-insensitivity of wormhole routing, these new algorithms often differ fundamentally from their store-and-forward counterparts. We examine software and hardware approaches to implementing collective communication operations. Although we emphasize methods in which the underlying architecture is a direct network, such as a hypercube or mesh, as opposed to an indirect switch-based network, several approaches apply to systems of either type. We illustrate several issues arising in this research area and describe the major classes of algorithms proposed to solve these problems.

Placement and routing tools for the Triptych FPGA

Abstract: Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications.

Hexagonal field programmable gate array architecture

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

Predictive Q-Routing: A Memory-based Reinforcement Learning Approach to Adaptive Traffic Control

Abstract: In this paper, we propose a memory-based Q-Iearning algorithm called predictive Q-routing (PQ-routing) for adaptive traffic control. We attempt to address two problems encountered in Q-routing (Boyan & Littman, 1994), namely, the inability to fine-tune routing policies under low network load and the inability to learn new optimal policies under decreasing load conditions. Unlike other memory-based reinforcement learning algorithms in which memory is used to keep past experiences to increase learning speed, PQ-routing keeps the best experiences learned and reuses them by predicting the traffic trend. The effectiveness of PQ-routing has been verified under various network topologies and traffic conditions. Simulation results show that PQ-routing is superior to Q-routing in terms of both learning speed and adaptability.

An efficient, fully adaptive deadlock recovery scheme: DISHA

Abstract: This paper presents a simple, efficient and cost effective routing strategy that considers deadlock recovery as opposed to prevention. Performance is optimized in the absence of deadlocks by allowing maximum flexibility in routing. Disha supports true fully adaptive routing where all virtual channels at each node are available to packets without regard for deadlocks. Deadlock cycles, upon forming, are efficiently broken by progressively routing one of the blocked packets through a deadlock-free lane. This lane is implemented using a central "floating" deadlock buffer resource in routers which is accessible to all neighboring routers along the path. Simulations show that the Disha scheme results in superior performance and is extremely simple, ensuring quick recovery from deadlocks and enabling the design of fast routers.

Circuit routing structure using fewer variable masks

Abstract: A structure for routing connections in a semiconductor circuit constructed on a silicon wafer substrate, and a method for making that structure. The routing structure is constructed using two layers of electrical conductors and a set of interlayer connectors, but one of the electrical connection layers is predetermined and need not be programmable. The fixed electrical connection layer is laid out with a plurality of preselected routing connections, such as a set of horizontal or "east-west" connections laid out in a predetermined pattern. The variable electrical connection layer is programmed to make use of the preselected routing connections to connect disparate locations within the circuit on the semiconductor wafer, such as by making vertical or "north-south", and also horizontal, connections to selected horizontal connectors. The pattern of horizontal connections comprises a plurality of horizontal lines, with vertical spacing between pairs of neighboring lines. Each line comprises a set of one or more horizontal segments, with each segment extending for a selected length, and with selected amounts of horizontal spacing between pairs of neighboring segments. Selected lines, such as those coupled to ground or power, may continue without breaks. Preferably, the spacing between lines, the length of each segment, and the spacing between segments are all preselected before construction of the semiconductor circuit.

Routing and wavelength assignment methods in single-hop all-optical networks with blocking

Abstract: We consider single-hop all-optical networks in which wavelength-routed connections (lightpaths) between source-destination pairs are dynamically established and torn down in response to a random pattern of arriving connection requests and connection holding times. A connection request may be blocked if no wavelength is available on a suitable path from source to destination. For these networks we consider several methods for routing and wavelength assignment which combine in various ways three main principles: wavelength reservation, protecting threshold and alternate routes. The methods are evaluated and compared in two case studies. In this type of network the traffic over lightpaths consisting of multiple links is susceptible to high blocking probabilities, which can interfere with the quality of service requirements. It is shown that some of the routing and wavelength assignment methods studied have the potential to overcome this difficulty.

Frequency routing device having a wide and substantially flat passband

Abstract: An optical apparatus is provided that includes a first frequency routing device having at least one input port and P output ports, where P>2. A second frequency routing device is also provided that has P input ports and at least one output port. P optical paths couple the input port of the first frequency routing device to the output port of the second frequency routing device.

Performance analysis of mesh interconnection networks with deterministic routing

Abstract: This paper develops detailed analytical performance models for k-ary n-cube networks with single-hit or infinite buffers, wormhole routing, and the nonadaptive deadlock-free routing scheme proposed by Dally and Seitz (1987). In contrast to previous performance studies of such networks, the system is modeled as a closed queueing network that: includes the effects of blocking and pipelining of messages in the network; allows for arbitrary source-destination probability distributions; and explicitly models the virtual channels used in the deadlock-free routing algorithm. The models are used to examine several performance issues for 2-D networks with shared-memory traffic. These results should prove useful for engineering high-performance systems based on low-dimensional k-ary n-cube networks. >

ROMM routing on mesh and torus networks

Abstract: ROMM is a class of Randomized, Oblivious, Multi--phase, Minimal routing algorithms. ROMM routing offers a potential for improved performance compared to both fully randomized algorithms and deterministic oblivious algorithms, under both light and heavy loads. ROMM routing also offers close to best case performance for many common routing problems. In previous work, these claims were supported by extensive simulations on binary cube networks [30, 31]. Here we present analytical and empirical results for ROMM routing on wormhole routed mesh and torus networks. Our simulations show that ROMM algorithms can perform several representative routing tasks 1.5 to 3 times faster than fully randomized algorithms, for medium--sized networks. Furthermore, ROMM algorithms are always competitive with deterministic, oblivious routing, and in some cases, up to 2 times faster.

Adaptive routing mechanism for torus interconnection network

Abstract: A routing mechanism includes two acyclic non-adaptive virtual channels having two types of virtual channel buffers to store packets along deterministic virtual paths between nodes in an n-dimensional networked system, and an adaptive virtual channel having a third type of virtual channel buffer to store the packets along non-deterministic virtual paths between the nodes. The packets are routed between the nodes along either selected portions of the deterministic virtual paths or selected portions of the non-deterministic virtual paths based on routing information such that a packet is never routed on a selected portion of one of the non-deterministic virtual paths unless the third type virtual channel buffer associated with the selected portion of the one non-deterministic virtual path has sufficient space available to store the entire packet.

Improved bounds for all optical routing

Abstract: We consider the ploying all optica P roblem of routing in networks emrouting technology. In these networks, messages travel in optical form and switchin is f! erformed directly on the optical signal. By using %. iferent uravelengths, several messages may use the same edge concurrently, Howeve!, messages assigned the same wavelength must use disjoznt paths, or else be routed at separate rounds. No bufferin at, intermediate nodes is available. Thus, routing in ing wavelengths, paths, and time slots messages. that For arbitrary bounded degree networks, we show any permutation can be routed efficiently in one round using at most 0(log2n/P2) wavelengths, where p is the edge expansion of the network. This improves a quadratic factor on previous results, and almost matches the R(1/P2) existential lower bound. We consider two of the more popular architectures for parallel corn uters. K For bounded dimension arrays we give the rst per-instance approximation algorithm. Given a limited number of wavelengths and a set, of messages to be routed, the algorithm approximates to within polylogarithmlc factors the optimal number of rounds necessary to route all messages. Previous results for arrays give on1 we show that on t K worst-case performance. Finally, e hypercube an be routed using only a constant num i: permutation can er of wavelengths. The previous known bound was O(log n).

Optimization method for routing and logical network design in multi-service networks

Abstract: A method is described for network optimization based on a multirate, circuit-switched analysis. Network loss probabilities are determined as a solution of a set of fixed point equations and the sensitivity of network performance, as a function of offered load and loss probabilities, is determined as a solution to a set of linear equations. Because the numerical complexity of solving both the fixed point equations and the sensitivity equations is of an order which renders an exact solution computationally intractable, an asymptotic approximation is applied which yields a solution to the network loss probabilities and network sensitivities. A global optimization procedure is then applied using an iterative, steepest ascent optimization procedure to yield a set of virtual path routings and capacity allocations.

Computational approaches to stochastic vehicle routing problems

Abstract: We report computational test results for several graph-based a priori heuristics for the Euclidean plane versions of two well-known stochastic optimization problems, the probabilistic traveling salesman problem (PTSP) and the probabilistic (or stochastic) vehicle routing problem (PVRP). These heuristics are termed a priori because they design vehicle routes prior to realization of demands. Our tests compare the quality of such solutions to sample averages of a posteriori solutions of the deterministic realizations—the underlying TSPs and VRPs. Our results indicate that the simplest implementations give average cost performance within 5% of the latter, while the best implementations show a gap of only about 1%. Since running times are modest, we conclude that the a priori approaches offer a large potential benefit to the practitioner seeking to obtain good performance in a situation where solving repeated deterministic instances of the TSP or VRP is impractical or otherwise undesirable.

The Triptych FPGA architecture

Abstract: Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.

Admission control and routing in ATM networks using inferences from measured buffer occupancy

Abstract: Addresses the issue of call acceptance and routing in ATM networks. The goal is to design an algorithm that guarantees bounds on the fraction of cells lost by a call. The method proposed for call acceptance and routing does not require models describing the traffic. Each switch estimates the additional fraction of cells that would be lost if new calls were routed through the switch. The routing algorithm uses these estimates. The estimates are obtained by monitoring the switch operations and extrapolating to the situation where more calls are routed through the switch. The extrapolation is justified by a scaling property. To reduce the variance of the estimates, the switches calculate the cell loss that would occur with virtual buffers. A way to choose the sizes of the virtual buffers in order to minimize the variance is discussed. Thus, the switches constantly estimate their spare capacity. Simulations were performed using Markov fluid sources to test the validity of the approach. >

Apparatus and method for partitioning resources for interconnections

Abstract: An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the device. If the requirements exceed the capacity, a larger device is necessary. Otherwise, a topmost interconnection level is established. This topmost level is partitioned into four different partitions. The components are assigned and optimized to these four partitions. Next, a lower level of interconnection is established for one or more of these four partitions. Each of these lower levels are, in turn, partitioned into four different partitions. Components are then assigned and optimized to these partitions. This process is repeated for even lower levels until routing of the interconnections for the system is achieved. Thereupon, the components are physically interconnected from the lower levels to the topmost level according to the routing pattern that was determined in the establishing, partitioning, and said optimizing steps.

Performance-oriented placement and routing for field-programmable gate arrays

Abstract: This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.