Showing papers on "Routing (electronic design automation) published in 1996"

Design of logical topologies for wavelength-routed optical networks

Abstract: The problem of designing a logical topology over a wavelength-routed all-optical network (AON) physical topology is studied. The physical topology consists of the nodes and fiber links in the network. On an AON physical topology, we can set up lightpaths between pairs of nodes, where a lightpath represents a direct optical connection without any intermediate electronics. The set of lightpaths along with the nodes constitutes the logical topology. For a given network physical topology and traffic pattern, our objective is to design the logical topology and the routing algorithm so as to minimize the network congestion while constraining the average delay seen by a source-destination pair and the amount of processing required at the nodes (degree of the logical topology). Ignoring the delay constraints can result in fairly convoluted logical topologies with very long delays. On the other hand, in all our examples, imposing it results in a minimal increase in congestion. While the number of wavelengths required to imbed the resulting logical topology on the physical all optical topology is also a constraint in general, we find that in many cases of interest this number can be quite small. We formulate the combined logical topology design and routing problem described above as a mixed integer linear programming problem which we then solve for a number of cases of a six-node network. This programming problem is split into two subproblems: logical topology design, and routing. We then compare the performance of several heuristic topology design algorithms against that of randomly generated topologies, as well as lower bounds.

A large‐scale horizontal routing model to be coupled to land surface parametrization schemes

Abstract: The main focus of this paper is the time series analysis of the precipitation-runoff process with transfer functions. Starting from there, a horizontal routing model is constructed to be coupled to the existing land surface parametrization (LSP) schemes which provide the lower boundary conditions in numerical weather prediction and atmospheric general circulation models. As these models currently have a resolution of 10 km−300 km (what we some kind of arbitrary define as the “large scale”), it will be assumed that the horizontal routing process can be lumped as a linear time invariant system. While the main physical properties of the soil (temperature, moisture) and all physical processes (partition of the energy and water fluxes) have to be represented by an LSP scheme, the coupling with a simple routing scheme allows the direct comparison of predicted and measured streamflow data as an integrated quantity and validation tool for both, the atmospheric and the LSP model. The main task of the routing scheme is to preserve the horizontal travel time of water within each grid box as well as from grid box to grid box in the coupled model to first order, while the correct amount of runoff must be given by the LSP scheme. Inverse calculation also allows the direct estimation of runoff which should have been produced by an LSP scheme. As we don't want to deal with snow processes the scheme is applied from February to November. DOI: 10.1034/j.1600-0870.1996.t01-3-00009.x

Effects of wavelength routing and selection algorithms on wavelength conversion gain in WDM optical networks

Abstract: Wavelength-division multiplexing (WDM) technology is emerging as the transmission and switching mechanism for future optical mesh networks. In these networks it is desired that a wavelength can be routed without electrical conversions. Two technologies are possible for this purpose: wavelength selective cross-connects (WSXC) and wavelength interchanging cross-connects (WIXC), which involve wavelength conversion. It is believed that wavelength converters may improve the blocking performance, but there is a mix of results in the literature on the amount of this performance enhancement. We use two metrics to quantify the wavelength conversion gain: the reduction in blocking probability and the increase in maximum utilization, compared to a network without converters. We study the effects of wavelength routing and selection algorithms on these measures for mesh networks. We use the overflow model to analyze the blocking probability for wavelength-selective (WS) mesh networks using the first-fit wavelength assignment algorithm. We propose a dynamic routing and wavelength selection algorithm, the least-loaded routing (LLR) algorithm, which jointly selects the least-loaded route-wavelength pair. In networks both with and without wavelength converters the LLR algorithm achieves much better blocking performance compared to the fixed shortest path routing algorithm. The LLR produces larger wavelength conversion gains; however, these large gains are not realized in sufficiently wide utilization regions and are diminished with the increased number of fibers.

Computing approximate blocking probabilities for a class of all-optical networks

Abstract: We study a class of all-optical networks using wavelength-division multiplexing (WDM) and wavelength routing, in which a connection between a pair of nodes in the network is assigned a path and a wavelength on that path. Moreover, on the links of that path no other connection can share the assigned wavelength. Using a generalized reduced load approximation scheme we calculate the blocking probabilities for the optical network model for two routing schemes: fixed routing and least loaded routing.

Communications system using a central controller to control at least one network and agent system

Abstract: A communications system and method for automatically making telephone routing decisions with "global authority" based upon information gathered in real time from the entire communications system and global optimization criteria. The present invention permits unified central control and management for the entire system.

FPGA architecture with repeatable tiles including routing matrices and logic matrices

Abstract: An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

Routing on longest-matching prefixes

Abstract: This article describes the dynamic prefix tries, a novel data structure with algorithms for insertion, deletion, and retrieval to build and maintain a dynamic database of binary keys of arbitrary length. These tries extend the concepts of compact digital (Patricia) tries to support the storage of prefixes and to guarantee retrieval times at most linear in the length of the input key irrespective of the trie size, even when searching for longest-matching prefixes. The new design permits very efficient, simple and nonrecursive implementations of small code size and minimal storage requirements. Insert and delete operations have strictly local effects, and their particular sequence is irrelevant for the structure of the resulting trie, thus maintaining at all times the desired storage and computational efficiency. The algorithms have bees successfully employed in experimental communication systems and products for a variety of networking functions such as address resolution, maintenance and verification of access control lists, and high-performance routing tables in operating system kernels.

A New Generation of Vehicle Routing Research: Robust Algorithms, Addressing Uncertainty

Abstract: In recent years new insights and algorithms have been obtained for the classical, deterministic vehicle routing problem as well as for natural stochastic and dynamic variations of it These new developments are based on theoretical analysis, combine probabilistic and combinatorial modeling, and lead to new algorithms that produce near-optimal solutions, and a deeper understanding of uncertainty issues in vehicle routing In this paper, we survey these new developments with an emphasis on the insights gained and on the algorithms proposed

Routing and channel assignment for low power transmission in PCS

Abstract: There has been increased interest recently from military, civil, and commercial sectors in networks capable of self-organization. Routing and channel assignment for multi-hop communications in these networks are complex problems, given the interactions between the various transmissions, all of which must share some fixed bandwidth, and by the lack of a central controller. By enforcing a "reuse distance" similar to the frequency reuse factor in AMPS cellular service, we can route and assign channels to (place) arriving calls in a peer-to-peer network so as to significantly reduce power requirements and interference.

Performance of Alternate Routing Methods in All-Optical Switching Networks

Abstract: We study routing methods in all-optical switching networks. In all-optical switching networks, the connection with more hops encounters more call blocking, and it is especially true in optical networks with no wavelength conversions. We therefore consider an alternate routing method with limited trunk reservation in which connections with more hops are prepared more alternate routes. Through developing an approximate analytic approach, we show that our method keeps good performance when compared with the existing alternate routing methods, and also that the fairness among connections can be improved. Further performance improvement is investigated by introducing a wavelength assignment policy and a dynamic routing method. An effectiveness of the proposed method is investigated through simulation.

Integrated circuit cell architecture and routing scheme

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Optimized placement and routing of datapaths

Abstract: A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing space estimator. The datapath floorplanner allows the designer to establish and maintain during floorplannning operations datapath regions that include a number of datapath functions each. The datapath floorplanner creates the datapath regions from a netlist specifying logic cell instances and connectivity information, and from a plurality of tile files. A tile file is a structured description of a datapath function, describing the relative vertical and horizontal placement of all logic cell instances within the datapath function. There is one tile file for each unique datapath function. The datapath function instances then are associated with a particular tile file by the tile file list file. The datapath floorplanner uses the tile files to integrate the placement information with the specific function instances, and further allows the specification of clusters, function interleaving, and net side constraints per region. A datapath placer places the datapath functions in each region using the relative placement information and constraints. The routing space estimator estimates the space needed for routing a placed region. All of this information is interactively provided to the circuit designer so as to allow almost real time modification of datapath placement.

A new model for optimal routing and wavelength assignment in wavelength division multiplexed optical networks

Abstract: We consider the problem of routing and assignment of wavelength (RAW) in optical networks. Given a set of requests for all-optical connections (or lightpaths), the problem is to (a) find routes from the source nodes to their respective destination nodes, and (b) assign wavelengths to these routes. Since the number of wavelengths is limited, lightpaths cannot be established between every pair of access nodes. In this paper we first consider the dynamic RAW problem where lightpath requests arrive randomly with exponentially distributed call holding times. Then, the static RAW problem is considered which assumes that all the lightpaths that are to be set-up in the network are known initially. Several heuristic algorithms have already been proposed for establishing a maximum number of lightpaths out of a given set of requests. However most of these algorithms are based an the traditional model of circuit-switched networks where routing and wavelength assignment steps are decoupled. In this paper a new graph-theoretic formulation of the RAW problem, dubbed as layered-graph, has been proposed which provides an efficient tool for solving dynamic as well as static RAW problems. The layered-graph model also provides a framework for obtaining exact optimal solution for the number of requested lightpaths as well as far the throughput that a given network can support. A dynamic and two static RAW schemes are proposed which are based on the layered-graph model. Layered-graph-based RAW schemes are shown to perform better than the existing ones.

Integrated circuit layout routing using multiprocessing

Abstract: A multithreaded wavefront routing system for simultaneously planning routes for wiring a semiconductor chip surface. The surface has a plurality of grids located thereon, and routes are planned according to a predetermined netlist. The system steps across the surface from a first location to a second location in a wave-type pattern. The system sequentially steps through the grid arrangement on the chip surface and plans routing one grid at a time using a plurality of threaded processors. The system recognizes pins as it steps through grids and determines a plan for the current grid by evaluating current wire position, target pin location, and any currently planned routes, designating reserved locations wherein the route may be planned subsequent to the current grid, and establishing a wire direction for each wire traversing the current grid. The system plans wiring through grids using multiple threaded processors employing shared memory and a semi-hard coded rule based expert system applying heuristics by planning various routes based on current and potential wire locations. The system propagates wiring and performs memory bookkeeping functions. The system also has the capability to plan an additional route from one target pin toward a first pin. Meetings between routes are designated and resolved. Reservations may be established when a processor plans a route. Mutex locks may be utilized to avoid multiprocessor conflicts.

Proxies for anonymous routing

Abstract: Using traffic analysis, it is possible to infer who is talking to whom over a public network. This paper describes a flexible communications infrastructure, called onion routing, which is resistant to traffic analysis. Onion routing lies just beneath the application layer, and is designed to interface with a wide variety of unmodified Internet services by means of proxies. Onion routing has been implemented on a Sun Solaris 2.4; in addition, proxies for World Wide Web browsing (HTTP), remote logins (RLOGIN), e-mail (SMTP) and file transfers (FTP) have been implemented. Onion routing provides application-independent, real-time and bi-directional anonymous connections that are resistant to both eavesdropping and traffic analysis. Applications making use of onion routing's anonymous connections may (and usually should) identify their users over the anonymous connection. User anonymity may be layered on top of the anonymous connections by removing identifying information from the data stream. Our goal is anonymous connections, not anonymous communication. The use of a packet-switched public network should not automatically reveal who is talking to whom; this is the traffic analysis that onion routing complicates.

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Abstract: We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay trade-off curve. We achieve this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. This constraint allows efficient identification of optimal solutions while still providing a rich solution space. We also incorporate simultaneous wire sizing. Our technique consistently produces topologies equalling the performance of previous approaches with substantially less area overhead.

Automated call router system and method

Abstract: The automated call routing system and method which operates on a call routing objective of a calling expressed in natural speech of the calling party. The system incorporates a speech recognition function, as to which a calling party's natural-speech call routing objective provides an input (15), and which is trained to recognize a plurality of meaningful phrases (10), each such phrase being related to a specific call routing objective. Upon recognition of one or more of such meaningful phrases in a calling party's input speech, an interpretation function (20) then acts on such calling party's routing objective, request to either implement the calling party's requested routing objective, or to enter into a dialog (25), with the calling party to obtain additional information from which a sufficient confidence level can be attained to implement that routing objective.

Method for maintaining virtual local area networks with mobile terminals in an ATM network

Abstract: A method and system are provided for implementing virtual local area networks (VLANs) over ATM using LAN over ATM emulation technology. Server nodes which provide address registration/resolution and which enable multicast and broadcast routing on each VLAN are interconnected into multiple trees. The root server nodes of each tree are interconnected according to a hypercube topology. Data structures for maintaining the locations and routing information of mobile terminals is provided. Methods for constructing and updating the data structures when a mobile terminal moves from location to another also provided. Methods are also provided for routing packets using the data structures to and from mobile terminals.

Geographically mapped telephone routing method and system

Abstract: A method and system for direct routing of telephone calls made by a caller originating from within specific calling areas to one of a plurality of locations of a second party according to certain criteria established by the second party. This routing is accomplished based on the assignment of latitude and longitude coordinates to a potential caller's location. Once these coordinates are assigned to each of the potential callers, the second party's criteria is applied to assign the potential caller to a second party. Such criteria could be existence within a previously-defined geographic area, a custom defined geographic area, or through calculations such as the shortest distance between coordinate points. Once all such assignments have been made, a database is assembled to be used by a long distance carrier for direct routing of telephone calls from callers to an assigned second party.

Adaptive fault-tolerant deadlock-free routing in meshes and hypercubes

Abstract: We present an adaptive deadlock-free routing algorithm which decomposes a given network into two virtual interconnection networks, VIN/sub 1/ and VIN/sub 2/. VIN/sub 1/ supports deterministic deadlock-free routing, and VIN/sub 2/ supports fully-adaptive routing. Whenever a channel in VIN/sub 1/ or VIN/sub 2/ is available, it can be used to route a message. Each node is identified to be in one of three states: safe, unsafe, and faulty. The unsafe state is used for deadlock-free routing, and an unsafe node can still send and receive messages. When nodes become faulty/unsafe, some channels in VIN/sub 2/ around the faulty/unsafe nodes are used as the detours of those channels in VIN/sub 1/ passing through the faulty/unsafe nodes, i.e., the adaptability in VIN/sub 2/ is transformed to support fault-tolerant deadlock-free routing. Using information on the state of each node's neighbors, we have developed an adaptive fault-tolerant deadlock-free routing scheme for n-dimensional meshes and hypercubes with only two virtual channels per physical link. In an n-dimensional hypercube, any pattern of faulty nodes can be tolerated as long as the number of faulty nodes is no more than [n/2]. The maximum number of faulty nodes that can be tolerated is 2/sup n-1/, which occurs when all faulty nodes can be encompassed in an (n-1)-cube. In an n-dimensional mesh, we use a more general fault model, called a disconnected rectangular block. Any arbitrary pattern of faulty nodes can be modeled as a rectangular block after finding both unsafe and disabled nodes (which are then treated as faulty nodes). This concept can also be applied to k-ary n-cubes with four virtual channels, two in VIN/sub 1/ and the other two in VIN/sub 2/. Finally, we present simulation results for both hypercubes and 2-dimensional meshes by using various workloads and fault patterns.

Routing and admission control in general topology networks with Poisson arrivals

Abstract: Emerging high-speed networks will carry traffic for services such as video-on-demand and video teleconferencing that require resource reservation along the path on which the traffic is sent. High bandwidth-delay product of these networks prevents circuit rerouting, i.e., once a circuit is routed on a certain path, the bandwidth taken by this circuit remains unavailable for the duration (holding time) of this circuit. As a result, such networks will need effectiveroutingandadmission controlstrategies. Recently developed on-line routing and admission control strategies have logarithmic competitive ratios with respect to theadmission ratio(the fraction of admitted circuits). Such guarantees on performance are rather weak in the most interesting case where the rejection ratio of the optimum algorithm is very small or even 0. Unfortunately, these guarantees cannot be improved in the context of the considered models, making it impossible to use these models to identify algorithms that are going to perform well in practice. In this paper we develop routing and admission control strategies for a probabilistic model, where the requests for virtual circuits between any two points arrive according to a Poisson process and where the circuit holding times are exponentially distributed. Our model is close to the one that was developed to analyze and tune the (currently used) strategies for managing traffic in long-distance telephone networks. We strengthen this model by assuming that the rates of the Poisson processes (the “traffic matrix”) are unknown to the algorithm and are chosen by the adversary. Our strategy is competitive with respect to the expectedrejection ratio. More precisely, it achieves an expected rejection ratio of at mostR*+?, whereR* is the optimum expected rejection ratio. The expectations are taken over the distribution of the request sequences, and, whereris the maximum fraction of an edge bandwidth that can be requested by a single circuit. Our result should be viewed in the context of the previous competitive routing and admission control strategies that requirer?1/logn, but are not able to formally analyze the (intuitively clear) relation betweenrand the performance achievable in realistic situations.

Automatic synthesis of standard cell layouts

Abstract: A method for automatically synthesizing standard cell layouts(170) given a circuit netlist, a template describing the layout style and a set of process design rules (136) starts by numerating an ordered sequence of physical netlists from the logical netlist(138). Next, a netlist is selected from the ordered sequence of physical netlists (140). Components are placed according to the selected physical netlist (144). The components are routed to implement interconnections specified by the netlist (154). The components are compacted (156). A next netlist is selected from the ordered sequence of physical netlists. The steps of placing, routing and compacting the components are repeated. The layout with the smallest width is selected(166). Finally, ies, contacts and vias are added and notches filled (170) to improve yield and performance of the circuit.

Method and apparatus for managing virtual circuits and routing packets in a network/subnetwork environment

Abstract: A system for managing virtual circuits and determining proper routing of packets in a network environment. The network includes a connection-oriented subnetwork and an arrangement of routers coupled to the connection-oriented subnetwork. The system determines paths to each exit router by considering all possible paths through the connection-oriented subnetwork. The system also determines paths to each exit router by considering existing virutal circuits through the connection-oriented subnetwork. Finally, the system determines and establishes a most beneficial new virtual circuit for the network. Additionally, the rate at which new virtual circuits are established may be regulated by the system.

Efficient communication through networks

Abstract: A method and device that interrogates the availability of a called party before placing a communication from the calling party to the called party. A callback may be initiated so that both communications are completed simultaneously. The routing of communication may take place through any one of a number of different networks and at another time of the day, even if the caller does not otherwise have access to those networks.

Rules based electronic message management system

Abstract: A system for managing electronic messages (24) is disclosed. Recipients (22, 26, 28) of electronic messages may define a set of rules for accepting incoming messages. These rules are applied by a message distributor (18) at substantially the initial point of distribution so that delays in routing messages are reduced. Additionally, network (14) traffic may be reduced because message routing is more direct.

Method of routing an integrated circuit

Abstract: A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.

Flexible, high-performance static RAM architecture for field-programmable gate arrays

Abstract: A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.

Packing Steiner trees: a cutting plane algorithm and computational results

Abstract: In this paper we describe a cutting plane algorithm for the Steiner tree packing problem. We use our algorithm to solve some switchbox routing problems of VLSI-design and report on our computational experience. This includes a brief discussion of separation algorithms, a new LP-based primal heuristic and implementation details. The paper is based on the polyhedral theory for the Steiner tree packing polyhedron developed in our companion paper (this issue) and meant to turn this theory into an algorithmic tool for the solution of practical problems.