scispace - formally typeset
Search or ask a question

Showing papers on "Routing (electronic design automation) published in 1997"


01 Jan 1997
TL;DR: A packet delay improvement up to fourfold has been observed in the authors' simulations compared with shortest-path scheme, making multimedia tra c viable and a radio channel model has been included to investigate the impact of channel fading on their protocols.
Abstract: A clusterhead-token infrastructure for multihop,mobile wireless networks has been designed. Traditional routing algorithms in wireline networks are not feasible for mobile wireless environment due to the dynamic change in link connectivity. To gain better performance for clustered multihop, mobile wireless networks, routing must take into account radio channel access, code scheduling, and channel reservation. In this paper, we propose some heuristic routing schemes for clustered multihop, mobile wireless networks. A packet delay improvement up to fourfold has been observed in our simulations comparedwith shortest-path scheme, making multimedia tra c viable. A radio channel model has been included to investigate the impact of channel fading on our protocols. To reduce the run time, a parallel simulator has been designed. Speedups of up to tenfold have been observed on a 16 processor SP/2.

1,206 citations


Book ChapterDOI
01 Sep 1997
TL;DR: In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which the authors can compare and presents placement and routing results on a new set of circuits more typical of today's industrial designs.
Abstract: We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.

1,133 citations


Journal ArticleDOI
TL;DR: A tabu search heuristic for the vehicle routing problem with soft time windows, where lateness at customer locations is allowed although a penalty is incurred and added to the objective value.
Abstract: This paper describes a tabu search heuristic for the vehicle routing problem with soft time windows. In this problem, lateness at customer locations is allowed although a penalty is incurred and added to the objective value. By adding large penalty values, the vehicle routing problem with hard time windows can be addressed as well. In the tabu search, a neighborhood of the current solution is created through an exchange procedure that swaps sequences of consecutive customers (or segments) between two routes. The tabu search also exploits an adaptive memory that contains the routes of the best previously visited solutions. New starting points for the tabu search are produced through a combination of routes taken from different solutions found in this memory. Many best-known solutions are reported on classical test problems.

966 citations


Proceedings ArticleDOI
08 Jun 1997
TL;DR: This paper uses an approximation to the minimum connected dominating set (MCDS) of the ad-hoc network topology as the virtual backbone, and maintains local copies of the global topology of the network, along with shortest paths between all pairs of nodes.
Abstract: We impose a virtual backbone structure on the ad-hoc network, in order to support unicast, multicast, and fault-tolerant routing within the ad-hoc network. This virtual backbone differs from the wired backbone of cellular networks in two key ways: (a) it may change as nodes move, and (b) it is not used primarily for routing packets or flows, but only for computing and updating routes. The primary routes for packets and flows are still computed by a shortest-paths computation; the virtual backbone can, if necessary provide backup routes to handle interim failures. Because of the dynamic nature of the virtual backbone, our approach splits the routing problem into two levels: (a) find and update the virtual backbone, and (b) then find and update routes. The key contribution of this paper is to describe several alternatives for the first part of finding and updating the virtual backbone. To keep the virtual backbone as small as possible we use an approximation to the minimum connected dominating set (MCDS) of the ad-hoc network topology as the virtual backbone. The hosts in the MCDS maintain local copies of the global topology of the network, along with shortest paths between all pairs of nodes.

836 citations


Journal ArticleDOI
TL;DR: It is found that Internet paths are heavily dominated by a single prevalent route, but that the time periods over which routes persist show wide variation, ranging from seconds up to days.
Abstract: The large-scale behavior of routing In the Internet has gone virtually without any formal study, the exceptions being Chinoy's (1993) analysis of the dynamics of Internet routing information, and work, similar in spirit, by Labovitz, Malan, and Jahanian (see Proc. SIGCOMM'97, 1997). We report on an analysis of 40000 end-to-end route measurements conducted using repeated "traceroutes" between 37 Internet sites. We analyze the routing behavior for pathological conditions, routing stability, and routing symmetry. For pathologies, we characterize the prevalence of routing loops, erroneous routing, infrastructure failures, and temporary outages. We find that the likelihood of encountering a major routing pathology more than doubled between the end of 1994 and the end of 1995, rising from 1.5% to 3.3%. For routing stability, we define two separate types of stability, "prevalence", meaning the overall likelihood that a particular route is encountered, and "persistence", the likelihood that a route remains unchanged over a long period of time. We find that Internet paths are heavily dominated by a single prevalent route, but that the time periods over which routes persist show wide variation, ranging from seconds up to days. About two-thirds of the Internet paths had routes persisting for either days or weeks. For routing symmetry, we look at the likelihood that a path through the Internet visits at least one different city in the two directions. At the end of 1995, this was the case half the time, and at least one different autonomous system was visited 30% of the time.

811 citations


Proceedings ArticleDOI
22 Sep 1997
TL;DR: This work describes a self-organizing, dynamic spine structure within each lower level cluster to propagate topology changes, compute updated routes in the background, and provide backup routes in case of transient failures of the primary routes.
Abstract: We present a two-level hierarchical routing architecture for ad hoc networks. Within each lower level cluster, we describe a self-organizing, dynamic spine structure to (a) propagate topology changes, (b) compute updated routes in the background, and (c) provide backup routes in case of transient failures of the primary routes. We analyze and bound the worst case of movements between upper level clusters to show that this hierarchical architecture scales well with network size.

389 citations


Proceedings ArticleDOI
26 Sep 1997
TL;DR: This paper proposes and evaluates a Touting and addressing method to integrate geographic coordinates into the Internet Protocol to enable the creation of location dependent services.

371 citations


Patent
07 Nov 1997
TL;DR: In this article, a distributed computing system and methods to assign requests for data objects made by clients among multiple network servers are presented, in a manner that attempts to meet the goals of a particular routing policy.
Abstract: According to the present invention, a method and system provides the ability to assign requests for data objects made by clients among multiple network servers. The invention provides a distributed computing system and methods to assign user requests to replicated servers contained by the distributed computing system in a manner that attempts to meet the goals of a particular routing policy. Policies may include minimizing the amount of time for the request to be completed.

344 citations


Journal ArticleDOI
TL;DR: Simulation results over random networks show that unconstrained algorithms are not capable of fulfilling the QoS requirements of real-time applications in wide-area networks, and semiconstrained and constrained heuristics are capable of successfully constructing MC trees which satisfy the QS requirements ofreal-time traffic.
Abstract: Multicast (MC) routing algorithms capable of satisfying the quality of service (QoS) requirements of real-time applications will be essential for future high-speed networks. We compare the performance of all of the important MC routing algorithms when applied to networks with asymmetric link loads. Each algorithm is judged based on the quality of the MC trees it generates and its efficiency in managing the network resources. Simulation results over random networks show that unconstrained algorithms are not capable of fulfilling the QoS requirements of real-time applications in wide-area networks. Simulations also reveal that one of the unconstrained algorithms, reverse path multicasting (RPM), is quite inefficient when applied to asymmetric networks. We study how combining routing with resource reservation and admission control improves the RPM's efficiency in managing the network resources. The performance of one semiconstrained heuristic, MSC, three constrained Steiner tree (CST) heuristics, Kompella, Pasquale, and Polyzos (1992), constrained adaptive ordering (CAO), and bounded shortest multicast algorithm (BSMA), and one constrained shortest path tree (CSPT) heuristic, the constrained Dijkstra heuristic (CDKS) are also studied. Simulations show that the semiconstrained and constrained heuristics are capable of successfully constructing MC trees which satisfy the QoS requirements of real-time traffic. However, the cost performance of the heuristics varies. The BSMA's MC trees are lower in cost than all other constrained heuristics. Finally, we compare the execution times of all algorithms, unconstrained, semiconstrained, and constrained.

315 citations


Journal ArticleDOI
TL;DR: An ATM-based implementation of DT-DVTR in LEO satellite ISL networks is presented with some emphasis on the optimization alternatives, and the performance in terms of delay jitter is evaluated for an example ISL topology.
Abstract: Satellite systems are going to build a part of the future personal communications infrastructure. The first-generation candidates for satellite personal communication networks (S-PCN) will rely on low Earth orbit (LEO) and medium Earth orbit (MEO) constellations. A noticeable trend in this field is toward broadband services and the use of ATM. For LEO satellite systems employing intersatellite links (ISLs), this paper proposes an overall networking concept that introduces the strengths of ATM to their operation. The core of the paper is the design of a new routing scheme for the periodically time-variant ISL subnetwork, discrete-time dynamic virtual topology routing (DT-DVTR), and its ATM implementation. DT-DVTR works completely off line, i.e., prior to the operational phase of the system. In a first step, a virtual topology is set up for all successive time intervals of the system period, providing instantaneous sets of alternative paths between all source-destination node pairs. In the second step, path sequences over a series of time interval are chosen from that according to certain optimization procedures. An ATM-based implementation of DT-DVTR in LEO satellite ISL networks is presented with some emphasis on the optimization alternatives, and the performance in terms of delay jitter is evaluated for an example ISL topology.

265 citations


Patent
Allen Ginsberg1
09 Jun 1997
TL;DR: A call center for routing of a call from a user to one of a plurality of agent stations of an organization, comprises: an interactive graphical display of information relating to the organization, the display for showing status information of at least one agent station; a device for enabling the user to select an agent station from the display; and, a device to effecting a communications link between the caller and the agent station as mentioned in this paper.
Abstract: A call center for routing of a call from a user to one of a plurality of agent stations of an organization, comprises: an interactive graphical display of information relating to the organization, the display for showing status information of at least one agent station; a device for enabling a user to select an agent station from the display; and, a device for effecting a communications link between the caller and the agent station. Further included is a device for receiving information about the organization and updating the graphical display of information.

Proceedings ArticleDOI
Charles J. Alpert1, Anirudh Devgan1
13 Jun 1997
TL;DR: Weshow that using wire segmenting as a precursor to buffer insertion produces solutions within a few percent of optimal, while using only seconds of CPU time is shown.
Abstract: Buffer insertion seeks to place buffers on the wires of a signal netto minimize delay. Van Ginneken [Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay] proposed an optimal dynamicprogramming solution (with extensions proposed by [7] [8][9] [12]) such that at most one buffer can be placed on a singlewire. This constraint can hurt solution quality, but it may be circumventedby dividing each wire into multiple smaller segments.This work studies the problem of finding the correct number of segmentsfor each wire in the routing tree. Too few segments yieldssub-par solutions, but too many segments can lead to excessive runtimes and memory loads. We derive new theoretical results forcomputing the appropriate number of buffers (and hence wire segments)which motivate our new wire segmenting algorithm. Weshow that using wire segmenting as a precursor to buffer insertionproduces solutions within a few percent of optimal, while usingonly seconds of CPU time.

Journal ArticleDOI
TL;DR: An asynchronous transfer mode (ATM)-based concept for the routing of information in a low Earth orbit/medium Earth orbit (LEO/MEO) satellite system including intersatellite links (ISLs) is proposed, with specific emphasis on the design of an ATM-based routing scheme for the ISL part of the system.
Abstract: An asynchronous transfer mode (ATM)-based concept for the routing of information in a low Earth orbit/medium Earth orbit (LEO/MEO) satellite system including intersatellite links (ISLs) is proposed. Specific emphasis is laid on the design of an ATM-based routing scheme for the ISL part of the system. The approach is to prepare a virtual topology by means of virtual path connections (VPCs) connecting all pairs of end nodes in the ISL subnetwork for a complete period in advance, similar to implementing a set of (time dependent) routing tables. The search for available end-to-end routes within the ISL network is based on a modified Dijkstra (1959) shortest path algorithm (M-DSPA) capable of coping with the time-variant topology. With respect to the deterministic time variance of the considered ISL topologies, an analysis of optimization aspects for the selection of a path at call setup time is presented. The performance of the path search in combination with a specific optimization procedure is-by means of extensive simulations-evaluated for example LEO and MEO ISL topologies, respectively.

Proceedings ArticleDOI
05 May 1997
TL;DR: An automated design technique to reduce power by making use of two supply voltages by combining structure synthesis, placement and routing and random logic modules of a media processor chip.
Abstract: This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance,.

Journal ArticleDOI
TL;DR: In this paper, a parallel tabu search heuristic for solving the vehicle routing problem with time windows is developed and implemented on a network of workstations, and it is shown that parallelization of the original sequential algorithm does not reduce solution quality.
Abstract: The vehicle routing problem with time windows models many realistic applications in the context of distribution systems. In this paper, a parallel tabu search heuristic for solving this problem is developed and implemented on a network of workstations. Empirically, it is shown that parallelization of the original sequential algorithm does not reduce solution quality, for the same amount of computations, while providing substantial speed-ups in practice. Such speed-ups could be exploited to quickly produce high quality solutions when the time available for computing a solution is reduced, or to increase service quality by allowing the acceptance of new requests much later, as in transportation on demand systems.

Patent
Khue Duong1
10 Jan 1997
TL;DR: Signal routing resource tiles as discussed by the authors can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA).
Abstract: Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing.

Patent
06 Jan 1997
TL;DR: In this article, a computerized system and method for providing event-driven routing to provide user assistance and marketing functions in an order entry system is provided, where each of the application points is associated with at least one of the user-initiated events.
Abstract: A computerized system and method for providing event-driven routing to provide user assistance and marketing functions in an order entry system is provided. One or more user-initiated events capable of being recognized by the computer are defined, as are one or more application points. Each of the application points is associated with at least one of the user-initiated events. An action is assigned to each of the application points. The actions assigned to a particular application point are dynamically invoked upon initiation of the user-initiated event associated with that application point, so the user is provided with the action at a point during the placement of an order at which the action is needed.

Proceedings ArticleDOI
13 Nov 1997
TL;DR: A unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously, and is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.
Abstract: In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner trees or RATS-trees, providing a smooth trade-off among signal delay, waveform, and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.

Patent
Siamack Ayandeh1
29 Aug 1997
TL;DR: In this paper, the authors propose a distributed route server element (RSE) where the routing functions are distributed throughout the processing elements that constitute a switching node, while maintaining the global identity and routing information exchange functions of a RSE.
Abstract: A design for a network route server in which network routing functions are distributed throughout the processing elements that constitute a switching node, while maintaining the global identity and routing information exchange functions of a route server element (RSE). Intelligent line-cards are provided having the ability to route independently of the RSE. This removes the RSE as a bottleneck resource and ensures that the capacity of the switching node is limited only by the switching capacity of its switch fabric. The RSE serves the functions of network topology discovery and routing table construction using a network topology database and an optimal routing algorithm. Copies of the dynamically maintained routing tables are distributed to the intelligent line-cards on a periodic basis governed by predetermined criteria. Wider geographical distribution of the RSE is enabled and most efficient utilization of the switch fabric is ensured. Scaling of distributed switching architectures is also enabled. The advantage is a significant increase in switching capacity as well as an increased degree of network connectivity.

Posted Content
TL;DR: An algorithm for solving the problem of routing trains through a railway station in the Netherlands in terms of a Weighted Node Packing Problem is described, based on preprocessing, valid inequalities, and a branch-and-cut approach.
Abstract: In this paper we describe the problem of routing trains through a railway station. This routing problem is a subproblem of the automatic generation of timetables for the Dutch railway system. The problem of routing trains through a railway station is the problem of assigning each of the involved trains to a route through the railway station, given the detailed layout of the railway network within the station and given the arrival and departure times of the trains. When solving this routing problem, several aspects such as capacity, safety, and customer service have to be taken into account. In this paper we describe this routing problem in terms of a Weighted Node Packing Problem. Furthermore, we describe an algorithm for solving this routing problem to optimality. The algorithm is based on preprocessing, valid inequalities, and a branch-and-cut approach. The preprocessing techniques aim at identifying super uous nodes which can be removed from the problem instance. The characteristics of the preprocessing techniques with respect to propagation are investigated. We also present the results of a computational study in which the model, the preprocessing techniques and the algorithm are tested based on data related to the railway stations Arnhem, Hoorn and Utrecht in the Netherlands.

Proceedings ArticleDOI
01 Jul 1997
TL;DR: This study shows that routing queries learned only from the documents in a query domain are better than the routing profiles learned when query domains are not used, and approximate a querydomain by a guerg zone.
Abstract: Word usage is domain dependent. A common word in one domain can be quite infrequent in another. In this study we exploit th~ property of word usage to improve document routing. We show that routing queries (profiles) learned only from the documents in a query domain are better than the routing profiles learned when query domains are not used. We approximate a query domain by a guerg zone. Experiments show that routing profiles learned from a query zone are 8–12~0 more effective than the profiles generated when no query zoning is used.

Patent
20 Jun 1997
TL;DR: In this article, a method and structure for routing electrically conductive interconnect paths through a printed circuit board is presented, where a plurality of voltage supply pad patterns are located at the upper surface of the printed circuit boards.
Abstract: A method and structure for routing electrically conductive interconnect paths through a printed circuit board. The printed circuit board includes a plurality of insulating layers and conductive layers, including at least one electrically conductive voltage supply layer for receiving a first supply voltage. A plurality of voltage supply pad patterns are located at the upper surface of the printed circuit board. Each voltage supply pad pattern includes two or more electrically conductive pads which are coupled by one or more electrically conductive traces. Electrically conductive via plugs extend through the printed circuit board to connect the voltage supply layer to the voltage supply pad patterns. Each via plug is connected to one corresponding voltage supply pad pattern, thereby allowing each via plug to provide the first supply voltage to a plurality of pads at the upper surface of the printed circuit board. As a result, the number of via plugs required for routing the first supply voltage through the printed circuit board is reduced, thereby increasing the layout area available for routing conductive traces in other layers of the printed circuit board.

Patent
27 Oct 1997
TL;DR: In this article, a system for managing electronic messages is described, where recipients of electronic messages may define a set of rules for accepting incoming messages and these rules are applied by a message distributor at substantially the initial point of distribution so that delays in routing messages are reduced.
Abstract: A system for managing electronic messages is disclosed. Recipients of electronic messages may define a set of rules for accepting incoming messages. These rules are applied by a message distributor at substantially the initial point of distribution so that delays in routing messages are reduced. Additionally, network traffic may be reduced because message routing is more direct.

Journal ArticleDOI
TL;DR: For some time, the networking community has assumed that it is impossible to do IP routing lookups in software fast enough to support gigabit speeds, but research suggests that this assumption is wrong.
Abstract: For some time, the networking community has assumed that it is impossible to do IP routing lookups in software fast enough to support gigabit speeds. IP routing lookups must find the routing entry ...

Patent
02 Dec 1997
TL;DR: In this article, a direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device, which enables high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics.
Abstract: A direct connect mesh routing structure is provided for interconnecting configurable logic blocks within a programmable logic device. The structure includes multi-bit interconnect busses and a highly regular structure distributed throughout a configurable array enabling high direct interconnect utilization to adjacent and non-adjacent logic blocks, high speed circuit implementation, and improved timing characteristics. The direct connections of the invention are the preferred interconnect path between logic blocks because they substantially reduce the average interconnect delay, thereby allowing the programmable logic device to operate at a higher speed.

Patent
Howard A. Seid1
03 Jul 1997
TL;DR: In this article, the authors define a general additive operator which is able to add traditionally (arithmetic) additive cost factors and which takes into account cost factors which are not additive, the generally additive operator being defined such that distributive and communicative properties are applicable.
Abstract: Connectivity matrix-based multi-cost routing includes defining a generally additive operator which is able to add traditionally (arithmetic) additive cost factors and which takes into account cost factors which are not additive, the generally additive operator being defined such that distributive and communicative properties are applicable, and wherein the generally additive operator is applicable to connectivity matrix-based factors for determining the relative costs of paths within a network, particularly with respect to multi-cost factors. Connectivity matrix-based multi-cost routing is performed by first defining cost functions and establishing a criteria for prioritizing cost functions such that a composite multi-cost function includes the cost functions in the priority order defined by the criterion. A connectivity matrix is established including ordered n-tuples of cost factors corresponding to the priority established by the criterion, and a shortest path matrix determination is made by using the generally additive operator to apply the composite multi-cost function to the connectivity matrix. When links within a network support various functionality, a mask of a required functionality may be used to define a cost function for a given shortest path matrix determination. A correcting method is provided for a routing determination when, after a shortest path matrix determination, a routing choice is not provided which would otherwise satisfy a multi-cost requirement, the correcting method including the determination of a primary path and secondary paths between a source node and a destination node.

Patent
17 Nov 1997
TL;DR: A scalable multiprocessor system includes processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element node on the physical communication links as discussed by the authors.
Abstract: A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4×8×4 torus topology.

Patent
05 Nov 1997
TL;DR: In this paper, the authors propose a custom circuitry for an adaptive, RAM-based, hardware routing engine that conforms bit selection dynamically to information made available by a self-optimizing data hashing algorithm.
Abstract: Custom circuitry for an adaptive, RAM-based, hardware routing engine conforms bit selection dynamically to information made available by a self-optimizing data hashing algorithm. Circuitry includes a staggered multiplexor array for selecting bits from only the most distinctive bit positions of an inbound identifier to effectuate associative comparisons at approximately CAM speeds under perfect or near perfect hash conditions. The custom circuitry includes means for monitoring routing performance and instructing a processing element to correct the hashing algorithm when performance has sufficiently deteriorated. The custom circuitry also has an extended recursive look-up capability.

Patent
14 Nov 1997
TL;DR: In this article, a routing policy is defined at the dispatcher using at least one routing rule having a condition and an action, and each of the requests is routed to a destination by testing the current state information against the condition.
Abstract: A routing apparatus is located at an outbound “edge” of an administrative domain or at an inbound “edge” of an ISP or other network facility. The apparatus, which is preferably implemented in software, includes a “dispatcher.” The dispatcher has a database associated therewith in which information about a “current state” of the network or some resource therein is collected and maintained. The “current state” information is generally of two types: quality-of-service (Q-o-S) information associated with transactions involving a particular Web server, or more general network resource availability information. According to the invention, a routing “policy” is defined at the dispatcher using at least one routing rule having a condition and an action. As service requests arrive at the dispatcher, each of the requests is routed to a destination by testing the current state information against the condition.

Journal ArticleDOI
TL;DR: A technique to enhance multicomputer routers for fault-tolerant routing with modest increase in routing complexity and resource requirements is described, which handles solid faults in meshes.
Abstract: A technique to enhance multicomputer routers for fault-tolerant routing with modest increase in routing complexity and resource requirements is described. This method handles solid faults in meshes, which includes all convex faults and many practical nonconvex faults, for example, faults in the shape of L or T. As examples of the proposed method, adaptive and nonadaptive fault-tolerant routing algorithms using four virtual channels per physical channel are described.