Routing table

About: Routing table is a research topic. Over the lifetime, 16589 publications have been published within this topic receiving 336842 citations. The topic is also known as: routing information base & RIB.

Dynamically controlled routing using virtual nodes

Abstract: A dynamically controlled routing (DCR) telecommunications network is formed by a plurality of network switching elements, each connected to at least one other by at least one circuit group for carrying calls therebetween, and a network processor connected to the network elements by data links. Each network switching element determines, for each call, a neighboring network element to which it should be routed. It does so by accessing a routing table which contains alternate routes to be attempted if a direct route either does not exist or cannot be used. The routing tables are updated periodically by the network controller. The DCR network functions as a group of nodes interconnected by links and routing takes place on a node-to-node basis. At least one of the nodes is a logical entity which does not necessarily have a direct correspondence to a single physical network element but rather corresponds to a group of at least one physical component which may be a network element, a part of a network element, or a plurality of network elements or parts thereof. Likewise, a link to the virtual node does not necessarily correspond to a circuit group but comprises the set of direct circuit groups connecting to the components of the virtual node. DCR networks employing virtual nodes have increased flexibility. For example, final destinations outside the DCR network can be associated with the virtual node ifs an intermediate destination node, thereby allowing a call to exit the DCR network via any of the components of the virtual node rather than via only one Unique Exit Gateway.

Geographic Properties of Internet Routing

Abstract: In this paper, we study the geographic properties of Internet routing. Our work is distinguished from most previous studies of Internet routing in that we consider the geographic path traversed by packets, not just the network path. We examine several geographic properties including the circuitousness of Internet routes, how multiple ISPs along an end-to-end path share the burden of routing packets, and the geographic fault tolerance of ISP networks. We evaluate these properties using extensive network measurements gathered from a geographically diverse set of probe points. Our analysis shows that circuitousness of Internet paths depends on the geographic and network locations of the end-hosts, and tends to be greater when paths traverse multiple ISP. Using geographic information, we quantify the degree to which an ISP’s routing policy resembles hot-potato or cold-potato routing. We find evidence of certain tier-1 ISPs exhibiting hot-potato routing. Finally, based on network topology information gathered at CAIDA, we find that many tier-1 ISP networks may have poor tolerance to the failure of a single, critical geographic node, assuming the published topology information is reasonably complete.

Performance Analysis of Proactive and Reactive Routing Protocols for Ad hoc Networks

Abstract: Mobile Ad hoc networks are the collection of wireless nodes that can exchange information dynamically among them without pre existing fixed infrastructure. Because of highly dynamic in nature, performance of routing protocols is an important issue. In addition to this routing protocols face many challenges like limited battery backup, limited processing capability and limited memory resources. Other than efficient routing, efficient utilization of battery capacity and Security are also the major concern for routing protocols. This paper presents simulation based comparison and performance analysis on different parameters like PDF, Average e-e delay, Routing Overheads and Packet Loss. The study is about three main protocols DSR, AODV (Reactive) and DSDV (Proactive).

Using CPU as a traffic co-processing unit in commodity switches

Abstract: Commodity switches are becoming increasingly important as they are the basic building blocks for the enterprise and data center networks. With the availability of all-in-one switching ASICs, these switches almost universally adopt single switching ASIC design. However, such design also brings two major limitations, i.e, limited forwarding table for flow-based forwarding scheme such as Openflow and shallow buffer for bursty traffic pattern. In this paper, we propose to use CPU in the switches to handle not only control plane but also data plane traffic. We show that this design can provide large forwarding table for flow-based forwarding scheme and deep packet buffer for bursty traffic. We build such a prototype switch on ServerSwitch platform. In our evaluation, we show that our prototype can achieve over 90% traffic offloading ratio, absorb large traffic bursts without a single packet drop, and can be easily programmed to detect and defend low-rate burst attacks.

A Multicast Tree Router for Multichip Neuromorphic Systems

Abstract: We present a tree router for multichip systems that guarantees deadlock-free multicast packet routing without dropping packets or restricting their length. Multicast routing is required to efficiently connect massively parallel systems' computational units when each unit is connected to thousands of others residing on multiple chips, which is the case in neuromorphic systems. Our tree router implements this one-to-many routing by branching recursively-broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree's root. Deadlock is avoided by routing in two phases-an upward phase and a downward phase-and by restricting branching to the downward phase. This design is the first fully implemented wormhole router with packet-branching that can never deadlock. The design's effectiveness is demonstrated in Neurogrid, a million-neuron neuromorphic system consisting of sixteen chips. Each chip has a 256 × 256 silicon-neuron array integrated with a full-custom asynchronous VLSI implementation of the router that delivers up to 1.17 G words/s across the sixteen-chip network with less than 1 μs jitter.