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Showing papers on "Sampling (signal processing) published in 1978"


Journal ArticleDOI
S. Tewksbury1, R. Hallock1
TL;DR: The design of Nth-order oversampled coders and an experimental third-order predictive coder are described, allowing N+1/2 bits to be eliminated from the coder's A/D for each doubling of the sample rate.
Abstract: First-order predictive coders (e.g., DPCM) and first-order noise shaping coders (e.g, interpolative coders) are familiar A/D conversion techniques. Using a feedback network containing an A/D and a first-order (single-pole) analog filter, they reduce the number of A/D output levels, for a given SNR requirement, at the expense of the additional analog filter complexity. Oversampling (i.e., sampling at higher than the Nyquist rate) provides excess bandwidth in the feedback loop, allowing further reductions in the number of A/D output levels at the expense of faster circuitry. This paper extends such first-order oversampled coders to include higher order analog filters under the constraint that the filters be independent of the statistical properties of the input analog signal. The resulting robust Nth-order predictive and noise-shaping coders allow N+1/2 bits to be eliminated from the coder's A/D for each doubling of the sample rate. The design of such Nth-order oversampled coders and an experimental third-order predictive coder are described.

193 citations


Journal ArticleDOI
D. Godard1
TL;DR: Under conditions likely to be encountered on actual voiceband communication channels, the clock phase derived is shown to prevent spectral nulls and to accurately approximate the optimum timing phase for an infinite equalizer.
Abstract: The performance of conventional modem receivers, where adaptive equalization is achieved by a digital transversal filter with tap gains spaced at the symbol interval, depends critically on the choice of the sampling phase. In this paper, a digital timing recovery loop is described and analyzed in the case of passband quadrature amplitude modulated data signals. Under conditions likely to be encountered on actual voiceband communication channels, the clock phase derived is shown to prevent spectral nulls and to accurately approximate the optimum timing phase for an infinite equalizer. Computer simulations show that the proposed system is capable of fast timing acquisition.

163 citations


Journal ArticleDOI
TL;DR: This paper presents an implementation of a digital beamformer that achieves the desired synchronous beams while minimizing the sensor channel sampling rate requirement, and realizes a hardware savings since both A/D converter and cable bandwith requirements can be traded off against digital processing complexity to achieve an optimal partitioning.
Abstract: For many sonar applications, the sensor outputs of a hydrophone array are sampled at a rate significantly higher than that required for waveform reconstruction when digital beamforming is used. The reason for this is that the number of synchronous, or ’’natural,’’ beampointing directions is proportional to the beamformer input rate. This paper presents an implementation of a digital beamformer that achieves the desired synchronous beams while minimizing the sensor channel sampling rate requirement. The technique employs zero padding of sensor data followed by digital interpolation filters to achieve vernier beamformer delays. Interpolation filtering can be done either at the beamformer input or output to minimize processing requirements. The resulting structure realizes a hardware savings since both A/D converter and cable bandwith requirements can be traded off against digital processing complexity to achieve an optimal partitioning.

82 citations


PatentDOI
TL;DR: A system and method for speech recognition provides a means of printing phonemes in response to received speech signals utilizing inexpensive components and an algorithm for detecting major slope transitions of the analog speech signals.
Abstract: A system and method for speech recognition provides a means of printing phonemes in response to received speech signals utilizing inexpensive components. The speech signals are inputted into an amplifier which provides negative feedback to normalize the amplitude of the speech signals. The normalized speech signals are delta modulated at a first sampling rate to produce a corresponding first sequence of digital pulses. The negative feedback signal of the amplifier is delta modulated at a second sampling rate to produce a second sequence of digital pulses corresponding to amplitude information of the speech signals. The speech signals are filtered and utilized to produce a digital pulse corresponding to high frequency components of the speech signals having magnitudes in excess of a threshold voltage. A microprocessor contains an algorithm for detecting major slope transitions of the analog speech signals in response to the first sequence of digital signals by detecting information corresponding to presence and absence of predetermined numbers of successive slope reversals in the delta modulator producing the first sequence of digital pulses. The algorithm computes cues from the high frequency digital pulse and the second sequence of pulses. The algorithm computes a plurality of speech waveform characteristic ratios of time intervals between various slope transitions and compares the speech waveform characteristic ratios with a plurality of stored phoneme ratios representing a set of phonemes to detect matching therebetween. The order of comparing is determined on the basis of the cues and a configuration of a phoneme decision tree contained in the algorithm. When a matching occurs, a signal corresponding to the matched phoneme is produced and utilized to cause the phoneme to be printed. In one embodiment of the invention, the speech signals are produced by the earphone of a standard telephone headset.

60 citations


Journal ArticleDOI
TL;DR: Experimental results in a real complex environment consisting of a 1.544 Mbits/s T1 capacity digital link using QPSK modulation techniques, including both Gaussian and non-Gaussian perturbations, show pseudo-error detection to be reliable for the measurement of BER and for controlling channel switching.
Abstract: Pseudo-error detectors are devices which show great potential for the measurement of the bit error rate of an on-line digital communications link. They are implemented in the form of a second detector (in addition and in parallel to the traffic data bit detector) which is very perturbation-sensitive. They do not compromise the traffic handling capacity of the system. Four methods of generating the pseudo-error characteristic are described: i) shifted detection threshold; ii) intersymbol interference enhancement; iii) noise addition; iv) sampling phase offset. Practical considerations generally govern the choice of method. Experimental results of pseudo-error detector behavior in the presence of Gaussian noise show that stable characteristics can be achieved to estimate a wide range of bit error rate (BER's) in very modest time intervals. In addition, experimental results in a real complex environment consisting of a 1.544 Mbits/s T1 capacity digital link using QPSK modulation techniques, including both Gaussian and non-Gaussian perturbations, show pseudo-error detection to be reliable for the measurement of BER and for controlling channel switching.

33 citations


Patent
21 Feb 1978
TL;DR: In this article, a window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal, which provides a "window" output signal.
Abstract: A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The dual input configuration includes first and second pairs of differential transistors which are coupled to a differential regenerative and latching pair of transistors. The regenerative and latching transistor pair provides an output signal having first or second states only upon the required clock signal being applied to a current switching transistor pair. Negative differential signals applied to both first and second pairs of differential transistors results in a "0" logic state output signal from the regenerative and latching transistors. A positive differential signal results in a logic "1" output state. Positive input signals applied to both differential transistors results in a logic "0" output state. Thus the latch network provides a "window" output signal.

29 citations


Patent
Thomas E. Hendrickson1
26 Jun 1978
TL;DR: In this paper, a signal processor for operating on signals provided by a photodetector, particularly arrays thereof, for use in image processing is described. But the processor is particularly well implemented by use of charge-coupled device technology for sampling and processing the photodeter signals.
Abstract: A signal processor is disclosed for operating on signals provided by a photodetector, particularly photodetectors, or arrays thereof, for use in image processing. The processor is particularly well implemented by use of charge-coupled device technology for sampling and processing the photodetector signals. The photodetector signals are sampled many times in a frame to provide a combined result representation of an image element in that frame to thereby reduce noise associated therewith.

28 citations


Patent
10 Aug 1978
TL;DR: In this paper, an input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency, and the resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto.
Abstract: An input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency. The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto. Waveforms are then displayed which correspond to these frequency and amplitude values. Various input and display circuits facilitate the display and interpretation of these waveforms.

27 citations


Journal ArticleDOI
TL;DR: A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise and an upper-bound to the model gain and to the pull-in range is obtained.
Abstract: A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise. The cycle slipping and the limit cycles phenomena are investigated. An upper-bound to the model gain and, consequently, to the pull-in range is obtained. Also a closed-form expression of acquisition time is derived. Moreover, using a random-walk model, the stationary phase error variance, the mean acquisition time and the mean first slip time have been evaluated. Some two channel configurations are proposed, which allow us to obtain a faster acquisition. Finally the problems relevant to the practical implementation of the loop are analyzed.

27 citations


Patent
10 Aug 1978
TL;DR: In this paper, an input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency, and the resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto.
Abstract: An input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency. The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto. Waveforms are then displayed which correspond to these frequency and amplitude values. Various input and display circuits facilitate the display and interpretation of these waveforms.

24 citations


Patent
22 Mar 1978
TL;DR: Disclosed as mentioned in this paper is a multichannel display device which is constructed so that the waveform of input signal of each channel displayed on the cathode ray tube can be enlarged or reduced in the horizontal sweep direction or the horizontal direction by setting a sampling time interval for sampling the input signal, storing the same in a corresponding one of plural memory units provided for each channel, and reading time for reading a sampled data stored in the corresponding memory.
Abstract: Disclosed is a multichannel display device which is so constructed that the waveform of input signal of each channel displayed on the cathode ray tube may be enlarged or reduced in the horizontal sweep direction or the horizontal direction by setting a sampling time interval for sampling the input signal of the channel to store the same in a corresponding one of plural memory units provided for each channel, a reading time for reading a sampled data stored in the corresponding memory, and a horizontal sweeping speed or one-sweep time of a cathode ray tube for displaying the waveform of the input signal in accordance with the sampled data as read, so as to permit these three factors to have an interrelation determined with respect to the channel

Patent
Kenneth F. Koch1, Louis E. Wessler1
23 Jun 1978
TL;DR: An automatic gain control circuit for controlling the gain of a video amplifier of the type adapted to amplify a composite video signal was proposed in this article, where the gain control signal was coupled to a control input of the video amplifier in order to maintain the actual potential difference between the sampled first and second portions with a predetermined reference potential.
Abstract: An automatic gain control circuit for controlling the gain of a video amplifier of the type adapted to amplify a composite video signal comprised of a video data component and a synchronization component. The circuit comprises first means coupled to the output of the video amplifier for sampling the voltage level of the amplified composite video signal during a first portion (e.g. backporch) of the synchronization component. Second means is coupled to the output of the video amplifier for sampling the voltage level of the amplified composite video signal during a second portion (e.g. tip) of the synchronization component. Third means is coupled to the first and second means for comparing the actual potential difference between the sampled first and second portions with a predetermined reference potential and for generating a gain control signal representative of such comparison. Fourth means is provided for coupling the gain control signal to a control input of the video amplifier in order to control the gain thereof to maintain the actual potential difference between the first and second portions proportional to the level of the predetermined reference potential.

Journal ArticleDOI
TL;DR: Communication technology has been applied to a magnetic disk recording channel to achieve up to a fourfold increase in linear bit density as compared to conventional binary recording.
Abstract: Communication technology has been applied to a magnetic disk recording channel to achieve up to a fourfold increase in linear bit density as compared to conventional binary recording. Among the techniques incorporated were digital data transmission by Class IV Partial-Response signaling (Interleaved NRZI), recording channel pre-emphasis, equalization and filtering, and periodic amplitude sampling of the data signal. The magnetic recording channel was linearized using very high frequency a.c. bias, which also served simultaneously to erase old data. This enabled multilevel recording and the addition of a pilot tone for timing recovery. System block diagrams are presented together with a discussion of the optimization procedure and attained system performance.

Patent
LeRoy D. Barter1
28 Feb 1978
TL;DR: In this article, a first counter for counting pulses from a digital clock for successive samplings of the analog signal to convert each sample into digital form and a counting register into which the pulse count in the first counter is transferred to be recounted at a later sampling.
Abstract: Apparatus for detecting a peak value of an analog signal includes a first counter for counting pulses from a digital clock for successive samplings of the analog signal to convert each sample of the analog signal into digital form and a counting register into which the pulse count in the first counter is transferred to be recounted at a later sampling. With a prior digital count in the register, the digital clock simultaneously (1) increments the counter to count the current signal sampling and (2) decrements the register to zero to recount the prior signal sampling. The counter is constrained to count up until both counting and recounting steps are complete before the count in the counter is transferred to the register. In this manner the counter will always attain the greater of the current and the prior sampling pulse count values and this maximum value will always be transferred into the register. A peak is signaled when the prior maximum pulse count exceeds current pulse counts for a predetermined number of successive samplings.

Patent
30 Jan 1978
TL;DR: In this article, a circuit is provided for monitoring a signal generated by an oscillator and producing a digital display of the sign and magnitude of the deviation of the actual frequency of the oscillator-generated signal from a preselected desired frequency.
Abstract: A circuit is provided for monitoring a signal generated by an oscillator and producing a digital display of the sign and magnitude of the deviation of the actual frequency of the oscillator-generated signal from a preselected desired frequency. Alternating sampling and display period pulses are produced in the circuit and, during the period of a sampling pulse, clock pulses are produced at a rate proportional to the actual frequency of the oscillator-generated signal. A plurality of counters in the circuit count the number of clock pulses produced during the period of a sampling pulse and hold the count during the period of a display pulse succeeding the sampling pulse. Read only memory devices sense the count held by the counters and decode the count to drive display units either to display the magnitude and sign of the deviation when it is within a predetermined range or to display an out-of-range indication.

Patent
21 Aug 1978
TL;DR: In this paper, a sampling linearizer including a phase shifter for use in improving the accuracy of an FM generated waveform with respect to a desired frequency rate of change is disclosed, which includes an oscillator for generating a reference frequency signal; a mixer governed by the generated FM waveform signal and the reference frequency signals to generate a first signal which is sampled at predetermined sampling times.
Abstract: A sampling linearizer including a phase shifter for use in improving the accuracy of an FM generated waveform with respect to a desired frequency rate of change is disclosed. The sampling linearizer comprises an oscillator for generating a reference frequency signal; a mixer governed by the generated FM waveform signal and the reference frequency signal to generate a first signal which is sampled at predetermined sampling times; and a linearizing servo controller which is governed by the sampled signal to reduce the inaccuracies in the genereated FM waveform with respect to the desired frequency rate of change. The sampling linearizer further includes a phase shifter disposed between the oscillator and mixer thereof and operative upon the reference frequency signal to generate another signal, the phase shifter being operative to shift the phase of the another signal with respect to the reference frequency signal as governed by a sequence of control signals representative of predetermined phase shift values. Each resulting phase shift causes the first signal to have a common reference value, preferably zero, concurrent with the predetermined sampling times when the frequency rate of change of the generated FM waveform is changing substantially at the desired rate and causes the first signal to have a phase error with respect to the common reference value concurrent with the sampling times when the frequency of the generated FM waveform is not changing substantially at the desired rate. This sampled phase error first signal is representative of the inaccuracies of the generated FM waveform and is used to govern the linearizing servo controller which regulates the FM waveform generator to reduce these frequency inaccuracies and maintain the frequency of the generated FM waveform substantially at the desired rate of change.

Patent
01 May 1978
TL;DR: In this article, a multichannel coherent receiver employing multiple delay lines in series or a tapped delay line into which a received signal band is introduced is introduced, where the signal band at each tap or increment of delay is mixed with individual related frequencies and the product from the mixers summed and further mixed with the output of a swept oscillator.
Abstract: A multichannel coherent receiver employing multiple delay lines in series or a tapped delay line into which a received signal band is introduced. The signal band at each tap or increment of delay is mixed with individual related frequencies and the product from the mixers summed and further mixed with the output of a swept oscillator. The composite delayed signal band is introduced into a bank of dispersive filters followed by means for deriving in-phase and quadrature components. Signals contained within the signal band may then be detected resulting in coherent channelization, improved frequency resolution and full time coverage sampling.

Patent
20 Sep 1978
TL;DR: In this paper, a method and apparatus for inductive flow measurement using a periodically reversed magnetic field, in which the useful signal is obtained by sampling and storing the signal voltage at equal but opposite values of induction of magnetic field and forming the difference of the stored sample values.
Abstract: Method and apparatus for inductive flow measurement using a periodically reversed magnetic field, in which the useful signal is obtained by sampling and storing the signal voltage at equal but opposite values of induction of magnetic field and forming the difference of the stored sample values. There is formed between each two successive magnetic field impulses of opposite polarity an interval where the magnetic field is zero, there being generated in a compensation time interval within each magnetic field interval at the same time-interval before the next subsequent sampling of the signal voltage, a compensation voltage which restores the signal voltage during the compensation time interval to zero value. The compensation voltage value developed during the compensation time interval is stored and is employed until the next compensation time interval.

Patent
10 Aug 1978
TL;DR: In this paper, an input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response to the input signal.
Abstract: An input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto Waveforms are then displayed which correspond to these frequency and amplitude values Various input and display circuits facilitate the display and interpretation of these waveforms

Patent
10 Aug 1978
TL;DR: In this paper, an input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency, and the resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto.
Abstract: An input signal is mixed with sampling signals from oscillators which vary the frequency of the sampling signal from a first frequency to a second frequency. The resulting Intermediate Frequency (IF) signal is processed and digital values are stored in a memory in response thereto. Waveforms are then displayed which correspond to these frequency and amplitude values. Various input and display circuits facilitate the display and interpretation of these waveforms.

Patent
22 Dec 1978
TL;DR: In this article, a system for digitally storing samples of an analog signal taken at a sampling rate, f, and for reconstructing said analog signal from such stored samples is presented, where the analog signal is separated into a plurality of, n, channels, each one of such channels having a digital storage section.
Abstract: A system for digitally storing samples of an analog signal taken at a sampling rate, f, and for reconstructing said analog signal from such stored samples. The analog signal is separated into a plurality of, n, channels, each one of such channels having a digital storage section. Each one of the storage sections is adapted to store a sample of the analog signal in response to a sampling pulse. A pulse generator circuit is provided and supplies one of a plurality of trains of periodic sampling pulses to a corresponding one of the plurality of storage sections. The sampling pulses in each of the trains of sampling pulses have a pulse repetition frequency, f/n. Further, the sampling pulses in successive trains thereof are delayed in time 1/nth the period of the sampling pulses. Apparatus is provided for retrieving the samples stored in the plurality of storage sections in the same sequence as such samples were stored. The sequentially retrieved samples are obtained at the rate, f, and are combined into a composite signal, such composite signal being a reconstruction of the analog signal. By using plural channels, each one of the storage sections samples the analog signal at a rate less than that required for a single channel system.

Patent
24 Mar 1978
TL;DR: In this article, a method and means for amplifying signal waves with high efficiency that comprises signal sampling means operating at the Nyquist rate or greater, sample-quantizing means, a plurality of circuits that link the quantizing means to the controlled current switching means, combining means that combines the outputs of the plurality of switching means and filter means that reconstructs an amplified facsimile of the signal.
Abstract: This invention provides a method and means for amplifying signal waves with high efficiency that comprises signal sampling means operating at the Nyquist rate or greater, sample-quantizing means, a plurality of circuits that link the quantizing means to a plurality of controlled current-switching means, combining means that combines the outputs of the plurality of switching means, and filter means that reconstructs an amplified facsimile of the signal.

Patent
22 Mar 1978
TL;DR: In this article, a sample and hold circuit is used to sample the magnitude of a reference voltage and a brightness representative blanking level of the video signal, and the control signal is applied to the signal channel for translating the blanking levels in a direction to minimize the voltage difference.
Abstract: Brightness control apparatus in a video system employing a sample and hold circuit including a charge storage capacitor. The sample and hold circuit forms a closed control loop with a signal processing channel, and is keyed during periodic blanking intervals of the video signal to sample the magnitude of a reference voltage and a brightness representative blanking level of the video signal. The sample and hold circuit provides an output control signal indicative of the voltage difference between the reference voltage and the blanking level. The control signal is applied to the signal channel for translating the blanking level in a direction to minimize the voltage difference, so that a desired relationship between the reference voltage and the blanking level is preserved. In a preferred embodiment, a diode coupled between a sampling transistor and the capacitor assures that the capacitor is not charged improperly in the event the normal current conducting mode of the transistor is disrupted in the presence of large amplitude video signals, thereby preventing operation of the closed control loop from being disrupted.

Patent
Hirashima Masayoshi1
01 Mar 1978
TL;DR: A sampling clock reproducing device was proposed in this article, where binary coded signals representative of letters or other patterns are superimposed on the television signal and the pilot signal is superimposed before the binary codes in order to indicate the phase thereof are received.
Abstract: A sampling clock reproducing device wherein binary coded signals representative of letters or other patterns which are superimposed on the television signal and the pilot signal superimposed before the binary coded signals in order to indicate the phase thereof are received, and the phase of the pilot signal is detected whereby clock pulses for sampling the binary coded signals are reproduced.

Patent
06 Oct 1978
TL;DR: In this article, the output of a horizontal frequency synchronizing pulse generator (E) is sampled at the vertical rate by a second sampling gate (106) controlled by a vertical rate signal.
Abstract: In a television camera system, a horizontal synchronizing signal from a reference source (100) is sampled at the vertical rate by a first sampling gate (104) controlled by a vertical rate signal from a reference source (102). A signal related to the output of a horizontal frequency synchronizing pulse generator (E) is sampled at the vertical rate by a second sampling gate (106) controlled by the vertical rate signal. The output of each sampling gate is fed to an input of a phase detector (114) which develops an error signal indicative of the phase relationship between the two sampled signals. The error signal is utilized to control the phase of the generated horizontal synchronizing pulse to synchronize a remote television camera head even though connected by a cable of unknown length.

Patent
Kozo Nakahata1
26 Jan 1978
TL;DR: In this article, a sample and hold circuit is provided to extract paired video signal values at paired points on the raster lines located symmetrically to each other relative to a vertical center line of the display screen.
Abstract: A raster, for example in magenta, generated on a phosphor screen of a color picture tube is picked up by a television camera through an optical filter which allows a magenta component to pass therethrough predominantly. The television camera scans the displayed raster in the horizontal direction on the line base thereby to produce a video signal representing luminances at individual points on the raster lines. A sample and hold circuit is provided to extract paired video signal values at paired points on the raster lines located symmetrically to each other relative to a vertical center line of the display screen. One of the paired video signal values extracted through the timed sampling operation is subtracted from the other at a processing circuit.

Patent
27 Jul 1978
TL;DR: In this article, a differential pulse code modulation (DPC) system is proposed, in which an input signal is at first approximated to a stepwise waveform having level changes at a constant number n of sampling points selected in the order of level magnitude from a predetermined number N of samples in the input signal.
Abstract: A differential pulse code modulation system, in which an input signal is at first approximated to a stepwise waveform having level changes at a constant number n of sampling points selected in the order of level magnitude from a predetermined number N of samples in the input signal. The remainder of the above approximating operation is secondary followed-up by delta modulation, which uses a variable step level controlled in accordance with the variation feature of the remainder. The differential pulse code modulation output is provided by the above two approximating operations.

Patent
05 Jul 1978
TL;DR: In this paper, the authors proposed to minimize even the horizontal shift of the liquid crystal TV screen and thus to enhance the picture quality by producing the sampling clock signals from the horizontal synchronous signals and then securing the synchronization for the sampling timing in each horizontal scanning.
Abstract: PURPOSE: To minimize even the horizontal shift of the liquid crystal TV screen and thus to enhance the picture quality by producing the sampling clock signals from the horizontal synchronous signals and then securing the synchronization for the sampling timing in each horizontal scanning. CONSTITUTION: Both the frequency and phase control are given to oscillation circuit 34 with the output of phase comparator 31 plus the output of subsequent LPF32. At the same time, the output of circuit 34 or the signal obtained by multiplying and dividing the output of 34 is drawn out in the form of sampling clock 38 of the video signal and horizontal synchronous oscillation output 37. With use of these signals, the synchronization is secured for the video signal sampling timing on each horizontal line, and also the timing has assured synchronization to the same picture element with each frame. As a result, the contour blur is reduced on the TV screen, at the same time enhancing the resolution greatly. COPYRIGHT: (C)1980,JPO&Japio

Patent
29 Nov 1978
TL;DR: In this paper, a sampling signal is generated which is adapted to have a frequency thereof deviated dependently upon an amount of wow and flutter caused by fluctuations in the speed of the relative motion therebetween.
Abstract: In the case that an analog signal is recorded or reproduced by using a sensor and recording medium relatively moving against the sensor, a sampling signal is generated which is adapted to have a frequency thereof deviated dependently upon an amount of wow and flutter caused by fluctuations in the speed of the relative motion therebetween. A reproduced signal is sampled by means of the sampling signal and, a sampled signal is stored in a memory. After this, a stored contents in the memory are read out by using a reading signal with a predetermined frequency, thereby to remove from the reproduced signal varying frequency components caused by the wow and flutter.

Patent
17 Nov 1978
TL;DR: The input data format in a single-sector or multi-sector scanner imaging system is chosen such that angulated scan lines intersect a lateral line at equal increments, and along the scan lines the echo signal is sampled at different rates whereby sampling points are along parallel raster lines Echo signals (1, 2, 3) from successive scan lines are stored (29, 31) in adjacent columns of a row-column oriented digital memory (30A-30D, 32) Echo data is read out (34A-34D, 35, 36, 37, 38) of memory row
Abstract: The input data format in a single-sector or multi-sector scanner imaging system is chosen such that angulated scan lines intersect a lateral line at equal increments, and along the scan lines the echo signal is sampled at different rates whereby sampling points are along parallel raster lines Echo signals (1, 2, 3) from successive scan lines are stored (29, 31) in adjacent columns of a row-column oriented digital memory (30A-30D, 32) Echo data is read out (34A-34D, 35, 36, 37, 38) of memory row by row at a variable rate to convert the read-out data back to sector geometry The image is displayed in real time on a cathode ray tube