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Scan chain

About: Scan chain is a research topic. Over the lifetime, 3021 publications have been published within this topic receiving 45219 citations.


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Proceedings ArticleDOI
08 May 1989
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Abstract: A set of 31 digital sequential circuits described at the gate level is presented. These circuits extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-based test generation, and mixed sequential/scan-based test generation using partial scan techniques. Although all the benchmark circuits are sequential, synchronous, and use only D-type flip-flops, additional interior faults and asynchronous behavior can be introduced by substituting for some or all of the flip-flops their appropriate functional models. The standard functional model of the D flip-flop provides a reference point that is independent of the faults particular to the flip-flop implementation. A testability profile of the benchmarks in the full-scan-mode configuration is discussed. >

1,972 citations

Journal ArticleDOI
Williams1, Parker
TL;DR: The different techniques of design for testability are discussed in detail, including techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.
Abstract: This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

428 citations

Journal ArticleDOI
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Abstract: A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.

417 citations

Proceedings ArticleDOI
30 Oct 2001
TL;DR: Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors, allowing for a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests.
Abstract: Rapid increases in the wire-able gate counts of ASICs stress existing manufacturing test equipment in terms of test data volume and test capacity. Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors. We show compression efficiencies allowing a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests. In addition, we obtain almost a 2/spl times/ scan test time reduction. By implementing these techniques for production testing of huge-gate-count ASICs, IBM will continue using existing automated test equipment (ATE)-avoiding costly upgrades and replacements.

368 citations

Journal ArticleDOI
TL;DR: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit.
Abstract: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops. >

346 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20235
202230
202131
202058
201959
201862