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Schottky barrier

About: Schottky barrier is a research topic. Over the lifetime, 22570 publications have been published within this topic receiving 427746 citations. The topic is also known as: Schottky barrier junction.


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Journal ArticleDOI
01 Jan 2006-Small
TL;DR: A generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described, and a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device is presented.
Abstract: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.

419 citations

Journal ArticleDOI
TL;DR: In this paper, a graphene-modified WO3/TiO2 step-scheme heterojunction composite photocatalyst was fabricated by a facile one-step hydrothermal method.

416 citations

Journal ArticleDOI
TL;DR: The fabrication of both n-type and p-type WSe2 field-effect transistors with hexagonal boron nitride passivated channels and ionic-liquid (IL)-gated graphene contacts is reported, indicating the possibility to utilize chemically or electrostatically highly doped graphene for versatile, flexible, and transparent low-resistance ohmic contacts to a wide range of quasi-2D semiconductors.
Abstract: We report the fabrication of both n-type and p-type WSe2 field-effect transistors with hexagonal boron nitride passivated channels and ionic-liquid (IL)-gated graphene contacts. Our transport measurements reveal intrinsic channel properties including a metal–insulator transition at a characteristic conductivity close to the quantum conductance e2/h, a high ON/OFF ratio of >107 at 170 K, and large electron and hole mobility of μ ≈ 200 cm2 V–1 s–1 at 160 K. Decreasing the temperature to 77 K increases mobility of electrons to ∼330 cm2 V–1 s–1 and that of holes to ∼270 cm2 V–1 s–1. We attribute our ability to observe the intrinsic, phonon-limited conduction in both the electron and hole channels to the drastic reduction of the Schottky barriers between the channel and the graphene contact electrodes using IL gating. We elucidate this process by studying a Schottky diode consisting of a single graphene/WSe2 Schottky junction. Our results indicate the possibility to utilize chemically or electrostatically high...

415 citations

Journal ArticleDOI
TL;DR: In this paper, the amplitude and phase of the electromagnetic radiation from the semiconductor surfaces depend on carrier mobility, impurity doping concentration, and strength and polarity of the static internal field.
Abstract: The basic concepts and preliminary applications of optically induced electromagnetic radiation from semiconductor surfaces and interfaces by using femtosecond optics are discussed. This submillimeter‐wave radiation provides a novel optoelectronic technique to study semiconductor electronic surface and interface properties with a contactless approach. The amplitude and phase of the electromagnetic radiation from the semiconductor surfaces depend on carrier mobility, impurity doping concentration, and strength and polarity of the static internal field. A large selection of bulk, epitaxial layer and superlattice samples from III‐V, II‐VI and group‐IV semiconductors has been tested. The orientation and strength of the static built‐in fields of a wide range of semiconductor surfaces, such as surface depletion, metal/semiconductor Schottky, p‐n junction and strain‐induced piezoelectric fields, can be determined and estimated.

412 citations

Journal ArticleDOI
TL;DR: In this article, the Schottky barrier is described by two fitting parameters that are the effective barrier heights ΦBeff and the ideality factors n. Due to lateral inhomogeneities of the barrier height, both parameters differ from one diode to another.
Abstract: Most metal–semiconductor contacts are rectifying. For moderately doped semiconductors, the current transport across such Schottky contacts occurs by thermionic emission over the Schottky barrier. The current–voltage characteristics of real Schottky contacts are described by two fitting parameters that are the effective barrier heights ΦBeff and the ideality factors n. Due to lateral inhomogeneities of the barrier height, both parameters differ from one diode to another. However, their variations are correlated in that ΦBeff becomes smaller with increasing n. Extrapolations of such ΦBeff-versus-n plots to the corresponding image-force-controlled ideality factors nif give the barrier heights of laterally homogeneous contacts. They are then compared with the theoretical predictions for ideal Schottky contacts. Data of Si, GaN, GaAs, and CdTe Schottky contacts reveal that the continuum of metal-induced gap states is the fundamental mechanism that determines the barrier heights. However, there are additional b...

411 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023565
2022988
2021672
2020758
2019824
2018847