Topic
Schottky barrier
About: Schottky barrier is a research topic. Over the lifetime, 22570 publications have been published within this topic receiving 427746 citations. The topic is also known as: Schottky barrier junction.
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TL;DR: The high stability in electronic performance of the devices upon bending up to ±2.2 mm in compressive and tensile modes, and the ability to recover electrical properties after degradation upon annealing, reveal the efficacy of using 2D materials for creating highly flexible and transparent devices.
Abstract: A highly flexible and transparent transistor is developed based on an exfoliated MoS2 channel and CVD-grown graphene source/drain electrodes. Introducing the 2D nanomaterials provides a high mechanical flexibility, optical transmittance (∼74%), and current on/off ratio (>10(4)) with an average field effect mobility of ∼4.7 cm(2) V(-1) s(-1), all of which cannot be achieved by other transistors consisting of a MoS2 active channel/metal electrodes or graphene channel/graphene electrodes. In particular, a low Schottky barrier (∼22 meV) forms at the MoS2 /graphene interface, which is comparable to the MoS2 /metal interface. The high stability in electronic performance of the devices upon bending up to ±2.2 mm in compressive and tensile modes, and the ability to recover electrical properties after degradation upon annealing, reveal the efficacy of using 2D materials for creating highly flexible and transparent devices.
274 citations
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TL;DR: In this article, a Schottky barrier on unintentionally doped n-type GaN grown by hydride vapor phase epitaxy was obtained and characterized using vacuum evaporated gold as the barrier contact and aluminum for the ohmic contact.
Abstract: A Schottky barrier on unintentionally doped n‐type GaN grown by hydride vapor phase epitaxy was obtained and characterized. Using vacuum evaporated gold as the Schottky barrier contact and aluminum for the ohmic contact, good quality diodes were obtained. The forward current ideality factor was n∼1.03 and the reverse bias leak current below 1×10−10 A at a reverse bias of −10 V. The barrier height φBn was determined to be 0.844 and 0.94 eV by current‐voltage and capacitance measurements, respectively.
273 citations
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TL;DR: In this article, it was shown that the effective height of a Schottky barrier can be controlled over a wide range using highly doped surface layers formed by low energy ion implantation.
Abstract: Using simplified models it is shown that the effective height of a Schottky barrier can be controlled over a wide range using highly doped surface layers. Experimental results on silicon having surface layers formed by low energy ion implantation verify the main features of the models and show that the use of surface layers brings flexibility to the Schottky barrier system.
272 citations
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TL;DR: In this paper, the Schottky barrier height of n-type β-Ga2O3 single crystals was determined by currentvoltage characteristics and high-resolution photoemission spectroscopy.
Abstract: The Schottky barrier height of Au deposited on (100) surfaces of n-type β-Ga2O3 single crystals was determined by current-voltage characteristics and high-resolution photoemission spectroscopy resulting in a common effective value of 1.04 ± 0.08 eV. Furthermore, the electron affinity of β-Ga2O3 and the work function of Au were determined to be 4.00 ± 0.05 eV and 5.23 ± 0.05 eV, respectively, yielding a barrier height of 1.23 eV according to the Schottky-Mott rule. The reduction of the Schottky-Mott barrier to the effective value was ascribed to the image-force effect and the action of metal-induced gap states, whereas extrinsic influences could be avoided.
272 citations
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02 Oct 2001
TL;DR: An integrated circuit with a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality with trench DMOS transistors within the transistor regions is described in this article, where the epitaxial layer has a lower doping level than the substrate.
Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
271 citations