Semiconductor device modeling

About: Semiconductor device modeling is a research topic. Over the lifetime, 2968 publications have been published within this topic receiving 44068 citations.

CMOS Circuit Speed and Buffer Optimization

Abstract: An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Abstract: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

Understanding MOSFET mismatch for analog design

Abstract: Despite the significance of matched devices in analog circuit design, mismatch modeling for design application has been lacking. This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, V/sub t/ and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOSFET current mirrors to show some nonobvious effects over bias, geometry, and multiple-unit devices.

Introduction to Semiconductor Materials and Devices

Abstract: BASIC PHYSICS. Review of Atomic Structure and Statistical Mechanics. Crystalline Solids and Energy Bands. FUNDAMENTALS OF SEMICONDUCTORS. Semiconductor Materials and Their Properties. Carrier Transport in Semiconductors. Excess Carriers in Semiconductors. JUNCTIONS AND INTERFACES. p-n Junctions. Static I-V Characteristics of p-n Junction Diodes. Electrical Breakdown in p-n Junctions. Dynamic Behavior of p-n Junction Diodes. Majority Carrier Diodes. SEMICONDUCTOR DEVICES. Microwave Diodes. Optoelectronic Devices. Bipolar Junction Transistors I: Fundamentals. Bipolar Junction Transistors II: Devices. Junction and Metal-Semiconductor Field-Effect Transistors. MOS Transistors and Charge-Coupled Devices. Circuit Models for Transistors. Power Rectifiers and Thyristors. SEMICONDUCTOR TECHNOLOGY AND MEASUREMENTS. Technology of Semiconductor Devices and Integrated Circuits. Semiconductor Measurements. Appendices. Answers to Selected Problems. Index.