Semiconductor memory

About: Semiconductor memory is a research topic. Over the lifetime, 45406 publications have been published within this topic receiving 663174 citations.

Digital integrated circuits: a design perspective

Abstract: (NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules-The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective-Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters-Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter-An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective-The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design-An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures

Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Three-Dimensional Optical Storage Memory

Abstract: A novel three-dimensional (3-D) optical memory device is presented that allows fast random access of the information and extremely high bit densities. This device is based on two-photon writing, reading, and erasing of the information in a photochromic material embedded in a polymer matrix. Absorption and emission data show that two-photon writing and reading of information is feasible. The advantages and properties of such a 3-D optical memory are discussed.

Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

Abstract: Today's electronic design and test engineers deal with several types of subsystems, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods. This book provides a careful selection of essential topics on all three types of circuits. The outcome of testing is product quality, which means "meeting the user's needs at a minimum cost". The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip.

Scalable high performance main memory system using phase-change memory technology

Abstract: The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.