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Sense amplifier

About: Sense amplifier is a(n) research topic. Over the lifetime, 19928 publication(s) have been published within this topic receiving 293776 citation(s).
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Journal ArticleDOI
Myoung-Jae Lee1, Chang Bum Lee1, Dongsoo Lee1, Seung Ryul Lee1  +9 moreInstitutions (2)
01 Aug 2011-Nature Materials
TL;DR: This work demonstrates a TaO(x)-based asymmetric passive switching device with which it was able to localize resistance switching and satisfy all aforementioned requirements, and eliminates any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

1,693 citations


Proceedings ArticleDOI
20 Jun 2009-
TL;DR: This paper analyzes a PCM-based hybrid main memory system using an architecture level model of PCM and proposes simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.
Abstract: The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

1,378 citations


Patent
17 Mar 2009-
Abstract: A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

1,212 citations


Journal ArticleDOI
Jonathan Green1, Jang Wook Choi1, Akram Boukai1, Yuri Bunimovich1  +11 moreInstitutions (4)
25 Jan 2007-Nature
TL;DR: A 160,000-bit molecular electronic memory circuit, fabricated at a density of 1011 bits cm-2 (pitch 33 nm; memory cell size 0.0011 μm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020.
Abstract: The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, [2]rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.

1,073 citations


Patent
11 Apr 1990-
Abstract: Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.

945 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20221
202177
2020177
2019164
2018156
2017253

Top Attributes

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Topic's top 5 most impactful authors

Frankie F. Roohparvar

63 papers, 1.5K citations

Daisaburo Takashima

32 papers, 592 citations

Frederick A. Perner

30 papers, 831 citations

Seong-Ook Jung

28 papers, 312 citations

Toshiaki Kirihata

21 papers, 378 citations