Topic
Sense amplifier
About: Sense amplifier is a research topic. Over the lifetime, 19928 publications have been published within this topic receiving 293776 citations.
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TL;DR: In this article, the authors examined two major causes of short memory retention: depolarization field and finite gate leakage current, and suggested a solution to the memory retention problem, which involves the growth of single-crystal, single domain ferroelectric on Si.
Abstract: In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.
431 citations
12 Jun 2012
TL;DR: The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density and Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
Abstract: Multi-core processor performance is limited by memory system bandwidth. The Hybrid Memory Cube is a three-dimensional DRAM architecture that improves latency, bandwidth, power and density. Through-silicon vias (TSVs), 3D packaging and advanced CMOS performance enable a new approach to memory system architecture. Heterogeneous die are stacked with significantly more connections, thereby reducing the distance signals travel.
423 citations
31 May 2011
TL;DR: This paper proposes a new hybrid design that features a hardware-driven page placement policy that is more robust and exhibits lower energy-delay2 than state-of-the-art hybrid systems.
Abstract: Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byte-addressable and exhibits access times in the nanosecond range, it can be used in main memory designs. In fact, PCM has higher density and lower idle power consumption than DRAM. Unfortunately, PCM is also slower than DRAM and has limited endurance. For these reasons, researchers have proposed memory systems that combine a small amount of DRAM and a large amount of PCM. In this paper, we propose a new hybrid design that features a hardware-driven page placement policy. The policy relies on the memory controller (MC) to monitor access patterns, migrate pages between DRAM and PCM, and translate the memory addresses coming from the cores. Periodically, the operating system updates its page mappings based on the translation information used by the MC. Detailed simulations of 27 workloads show that our system is more robust and exhibits lower energy-delay2 than state-of-the-art hybrid systems.
419 citations
TL;DR: In this article, the authors presented room-temperature operation for the first time of single-electron memory, in which one electron represents one bit of information, made possible by their new one-transistor memory configuration which has a very high charge sensitivity (conventionally, three circuit elements are needed).
Abstract: This paper presents room-temperature operation, for the first time, of single-electron memory, in which one electron represents one bit of information. This is made possible by our new one-transistor memory configuration which has a very high charge sensitivity (conventionally, three circuit elements are needed). Another new technique, which facilitates single-electron memory, is the ultra-thin (3.4 nm) poly-Si film used for the active region, in which sub-10-nm-width current channels and storage dots are naturally formed. In the fabricated poly-Si TFT's a single electron is stored (or "written") on a low-energy silicon island, and the number of stored electrons is counted (or "read") by the quantized threshold-voltage shift. Single-electron memory provides the potential for new nonvolatile RAM's, suitable for mobile computers/communicators. >
411 citations
TL;DR: A high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV, and the plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy.
Abstract: Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.
408 citations