Sequential decoding

About: Sequential decoding is a research topic. Over the lifetime, 8667 publications have been published within this topic receiving 204271 citations.

Approaching Capacity at High Rates With Iterative Hard-Decision Decoding

Abstract: A variety of low-density parity-check (LDPC) ensembles have now been observed to approach capacity with message-passing decoding. However, all of them use soft (i.e., non-binary) messages and a posteriori probability decoding of their component codes. In this paper, we show that one can approach capacity at high rates using iterative hard-decision decoding (HDD) of generalized product codes. Specifically, a class of spatially coupled generalized LDPC codes with Bose–Chaudhuri–Hocquengham component codes is considered, and it is observed that, in the high-rate regime, they can approach capacity under the proposed iterative HDD. These codes can be seen as generalized product codes and are closely related to braided block codes. An iterative HDD algorithm is proposed that enables one to analyze the performance of these codes via density evolution.

Mitigation of Impulsive Noise Effect on the PLC Channel With QC–LDPC Codes as the Outer Coding Scheme

Abstract: In this paper, the characteristics of irregular quasicyclic-low-density parity check (QC-LDPC) codes are examined when they are applied on a highly impulsive noise channel, such as the power-line-communications (PLC) channel. We study two decoding algorithms: 1) the sum product and 2) the bit-flipping algorithm, and how they affect the system's performance. LDPC codes are introduced in combination with other coding schemes, such as Reed-Solomon and convolutional codes. We propose irregular QC-LDPC codes as outer codes for the PLC channel in combination with Reed-Solomon codes, due to their decoding characteristics. In addition, various code rates are used for each different coding scenario. We also test how common Reed-Solomon codes affect the system's performance, such as the RS(63, 53), RS(511, 431), RS(127, 107), and RS(255, 239) codes. Furthermore, we propose an altered version of the sum-product decoding algorithm to enable its operation when QC-LDPC codes are used as the outer coding scheme in combination with Reed-Solomon codes. Regarding the system's design, the orthogonal frequency-division multiplexing transmission technique is utilized. We also take Zimmermann's model into consideration for the PLC channel and Middleton's noise model.

Viterbi convolutional coding method and apparatus

Abstract: A method and apparatus for executing a Viterbi decoding routine, in which the routine (input) is mapped to an array of interconnected reconfigurable processing elements (D). The processing elements function in parallel, and pass results to other processing elements to reduce the number of processing steps for executing the Viterbi decoding routine. Accordingly, the present invention may be used to perform the decoding routine with any number of constraint lengths and code rates, and be independent of a specific communication standard. Further, the present invention reduces power consumption and area in the use of circuits for performing the coding routine.

Sequential decoding for efficient communication from deep space

Abstract: A system based on sequential decoding and utilizing binary phase-shift keying and 8-level quantized decisions is proposed for deep-space communication. Theoretical analyses augmented by a program of computer Simulation promise operation within 3-4 dB of the channel capacity of an infinite bandwidth additive white Gaussian noise channel. A low probability of erasure is achieved by the suggested use of occasional off-line decoding. A negligible probability of error is readily achieved. Channel coherence is examined and quadratic and decision-directed methods of achieving a phase reference are compared. Extensive symbol interleaving is suggested and an analysis included of the required phase reference signal-to-noise ratio.

A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards

Abstract: In this paper, we propose a modified iterative decoding algorithm to decode a special class of quasi-cyclic low- density parity-check (QC-LDPC) codes such as QC-LDPC codes used in the IEEE 802.16e standards. The proposed decoding is implemented by serially decoding block codes with identical parity-check matrix H1 derived from the parity-check matrix H of the QC-LDPC codes. The dimensions of H1 are much smaller than those of H. Extrinsic values can be passed among these block codes since the code bits of these block codes are overlapped. Hence, the proposed decoding can reduce the number of iterations required by up to forty percent without error performance loss as compared to the conventional message- passing decoding algorithm. A partially-parallel very large-scale integration (VLSI) architecture is proposed to implement such a decoding algorithm. The proposed VLSI decoder can fully take advantage of the proposed decoding to increase its throughput. In addition, the proposed decoder only needs to store check-to- variable messages and hence is memory efficient.