Sequential decoding

About: Sequential decoding is a research topic. Over the lifetime, 8667 publications have been published within this topic receiving 204271 citations.

Decoding low-density parity-check codes with probabilistic scheduling

Abstract: We present a new message-passing schedule for the decoding of low-density parity-check (LDPC) codes. This approach, designated "probabilistic schedule", takes into account the structure of the Tanner graph (TG) of the code. We show by simulation that the new schedule offers a much better performance/complexity trade-off. This work also suggests that scheduling plays an important role in iterative decoding and that a schedule that matches the structure of the TG is desirable.

Algorithms and architectures for concurrent Viterbi decoding

Abstract: The sequential nature of the Vitterbi algorithm places an inherent upper limit on the decoding throughput of the algorithm in a given integrated circuit technology and thereby restricts its applications. Three methods of generating inherently unlimited concurrency in Viterbi decoding, for both controllable and uncontrollable shift register processes and Markov processes, are described. Concurrent decoders using these methods can apply high-throughput architectures with an overhead of pipeline latches or parallel hardware. A feasible method for bypassing the hardware limit is also proposed for decoding at an arbitrarily high as well as variable throughput. The proposed methods make real-time Viterbi decoding in the gigabit-per-second range feasible for convolutional and trellis codes. >

Method and system for decoding

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.

VLSI Structures for Viterbi Receivers: Part I--General Theory and Applications

Abstract: A taxonomy of VLSI grid model layouts is presented for the implementation of certain types of digital communication receivers based on the Viterbi algorithm. We deal principally with networks of many simple processors connected to perform the Viterbi algorithm in a highly parallel way. Two interconnection patterns of interest are the "shuffleexchange" and the "cube-connected cycles." The results are generally applicable to the development of area-efficient VLSI circuits for decoding: convolutional codes, coded modulation with multilevel/phase signals, punctured convolutional codes, correlatively encoded MSK signals and for maximum likelihood sequence estimation of M -ary signals on intersymbol interference channels. In a companion paper, we elaborate on how the concepts presented here can be applied to the problem of building encoded MSK Viterbi receivers. Lower bounds are established on the product (chip area) * (baud rate)-2and on the energy consumption that any VLSI implementation of the Viterbi algorithm must obey, regardless of the architecture employed or the intended application.

Two reliability-based iterative majority-logic decoding algorithms for LDPC codes

Abstract: This paper presents two novel reliability-based iterative majority-logic decoding algorithms for LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just as well as the existing weighted bit-flipping or other reliability-based iterative decoding algorithms for LDPC codes in error performance with a faster rate of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity.