Showing papers on "Serial port published in 1985"

Cascaded information processing module having operation unit, parallel port, and serial port for concurrent data transfer and data processing

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Automatic mode switching unit for a serial communications data system

Abstract: An automatic switching unit for use in combination with a backup processor and a series communications system such as for a retail store operation, and where the series communications system includes a controller having multiple serial ports, each port being connected in a series loop with a plurality of data terminals for registering sales transactions. The switching unit includes a monitor for monitoring each of the series loops to detect the malfunction of any port, and also includes a switching network. When the monitor detects a malfunction of any port, the switching network automatically connects the backup processor and all the data terminals in those loops associated with serial ports detected to be malfunctioning in a single series loop, and automatically disconnects the malfunctioning ports from the single series loop. In this way the backup processor is automatically substituted for the malfunctioning ports, and all the data terminals that had been connected to one or more series loops with the malfunctioning ports are automatically connected in a single series loop with the backup processor.

High speed RAM based data serializers

Abstract: Multiple bit parallel data serializers are described for accessing data serially through a port at high video data rates. The serializer preferably comprises a buffer array for storing data at a plurality of SRAM memory locations, sense amplifiers for sensing the stored data, an address decoder for selecting a predetermined memory location of the buffer array for data access by the sense amplifiers, a data latch for the latched buffering of data prior to output to the serial port and a control gate for enabling the gated transfer of data between the sense amplifiers and the output latch.

System for coupling a visual sensor processor and a robot controller.

Abstract: A system for coupling a visual sensor processor B and a robot controller A, in order to inexpensively constitute the whole system while maintaining increased processing speed. For this purpose, the visual sensor processor B and the robot controller A are couplped together through bidirectional high-speed data transfer channels (10, 28, /1, /2), so that the data required for the two apparatuses can be exchanged through these channels. Utilizing these channels, furthermore, a non-volatile memory (6) and serial interface (12) for connection to an external input/output device, installed in the robot controller A, are commonly used for these two apparatuses.

A Smart Crate Controller for Fast CAMAC Data Acquisition

Abstract: A smart CAMAC Crate Controller has been designed for use in Fermilab experiment E-705. Its distinctive feature is a hardwired list processor performing block transfers by executing lists of pre-stored CAMAC instructions. Data collected from the crate are sent to an external port: controllers organized in serial or parallel channels, transmit their data to buffer memories. Processing of interactive CAMAC operations, downloading of CAMAC instruction lists and supervision are provided by a Motorola 6809 micro-processor linked to the controller via the STD bus and to a host computer via an RS-232 serial interface.

A Fifth-Generation Routing Switcher Control System

Abstract: Over the years, routing switcher matrices have become larger and the control systems more complex. Control systems have evolved from simple wire-per-crosspoint designs to microprocessor-based designs. The use of microprocessors has produced powerful, flexible control systems, but at the same time, increases the difficulty of locating faults. This article describes a fifth-generation system that provides many functions that are indispensable for system maintenance and modification. The heart of the system is an RS-232 serial port dedicated to an installation/maintenance terminal. All installation-dependent information is contained in EEPROM. Thus, once configured via the terminal, these parameters are retained unless reconfigured.

Method for controlling joint-type robot

Abstract: PURPOSE: To control a robot at excellent response accuracy by providing an arithmetic processing function separate from the capacity receiving data transferred through a serial interface. CONSTITUTION: A CPUa with microprocessor constitution is connected to a data bus 10 and receives control target information supplied from a sensor system through the serial interface 11. An arithmetic processor CPUb if of the microprocessor constitution similar to the CPUa, and connected to the CPUa through a common memory 14. Accordingly a shift position data received as the control target information can be read out of the memory 14 by the CPUb, which converts inversely said information into correction data on each spindle of a joint robot. Then an action control program is generated which is corrected on the basis of a bubble memory 16 storing teaching data on standard work as a task program, and the action of the robot is controlled according to said program. COPYRIGHT: (C)1987,JPO&Japio

Circuit arrangement for remote data transfer checking

Abstract: A circuit arrangement (1) for checking remote data transmission, which is fitted between a data transmitting and/or receiving unit, for example a computer (4) or a terminal (7) and a modem (5) that can be connected to a data transmission line (6) or which is combined with the modem (5); the arrangement has a data buffer, a program memory, a microprocessor and a timer; a standard serial interface (V24) is used for connection of the unit transmitting and/or receiving the data and, when a separate modem (5) is used, a standard serial interface (V24) is also used for connecting said modem and an asynchronous transceiver is provided for connection of the standard serial interface(s) to the data bus of the microprocessor The microprocessor controls a character-orientated or block-orientated transmission, depending on the arrival of data, in each case preceded by an alignment bit, the addressing in the transmitter-side and receiver-side data buffers taking place synchronously and to indicate how much of a received message was recognised, an ACK/NACK character is transmitted After a number K of characters to be transmitted, the microprocessor sends a block check character BCC and, if characters to be transmitted are contained in the buffer memory, it effects transmission up to K characters and, if no correct message was last received and the previous character was a block check character, terminates the transmission

Modular business systems

Abstract: A computation and control module suitable for use in a variety of postal scales as well as other types of mailroom equipment is disclosed. The module includes a microprocessor (20) and associated circuitry; connectors (40, 50, 60) for connecting ROM, which store firmware for controlling the microprocessor, and PROM, which store postal rate charts; an input/output connector; a serial interface (90) for communications with postage meters; a non-volatile memory (110) for storing parameters specific to particular units; and an auxiliary input/output connector (110). The auxiliary input/output connector is driven by selected, memory mapped interface circuitry mounted on the PROM card. The module also includes a load cell interface (120) and a power supply (30). In one embodiment switches, responsive to the microprocessor, are provided for sequentially energizing various connectors and interfaces, so as to reduce power reqJirements. Systems comprising a plurality of computation and control modules are disclosed. Other systems including battery powered modules mechanically and electrically interconnected by a power distribution bus are also disclosed, as a modular power bus.

Radio data transmission equipment

Abstract: PURPOSE:To simplify the connection of a data terminal device by providing a storage section for data storage and a serial interface device for data terminal device connection to a radio equipment for MCA while they are connected to the equipment. CONSTITUTION:When the NCA radio equipment 11 receives a data registration request from the data terminal device 3 in case of entry of data from a mobile station to a center station, the serial data interface device 12 reads the data and checks parity and frame error at the same time. When no error exists, a CPU4 stores reception data in a memory 14. A control channel is acquired at normal end and a press-to-talk switch transmits a connection request signal to a control station. When a channel is moved to the talking channel, the central station is called, the data registered in the memory 14 is transmitted and the processing of data entry by the mobile station is finished.

Circuit switching devices

Abstract: Circuit switching devices (100, 200, 300) for switching a first serial interface having specifications different from those of the first serial interface that is designed to transfer the data which include digital binary series data, control signals and timing signals between an electronic equipment (105) and electronic equipment (205, 305) in the data transmission. First connectors (106, 206, 306) are mounted on interface boards (107, 207, 307) of the first serial interface of the electronic equipment (105, 205, 305). In this case, there are mounted, as a unitary structure, second connectors (102, 202, 302) that have the same terminal arrangement as the first connectors (106, 206, 306) and that can be directly inserted in the first connectors (106, 206, 306), and a plurality of third connectors (103a, 103b, 203a, 203b, 303a, 303b) that have a terminal arrangement adapted to the second serial interface. Transmission from the first serial interface to the second serial interface is controlled by control lines for data transmission of the first connectors (106, 206, 306).

Buffer device for host computer

Abstract: PURPOSE:To shorten the waiting time and transmission time of a host computer by using the 1st serial I/O part and parallel input part connected to the host computer and the 2nd serial I/O part and parallel output part connected to an external apparatus. CONSTITUTION:When the host computer outputs data used for a printer, a buffer device 1 stores parallel data 15 in a memory 13 through a CPU14. Then, parallel output data 19 are transmitted from the parallel output part 12 to the printer on the basis of a printer ready signal 17. When the host computer outputs data used for an external serial connection apparatus, the operation is decided in accordance with the length of the data outputted from the host computer. When the data outputted from the host computer is short, serial data 16 are inputted to the 1st serial I/O part 9. When the data outputted from the host computer is long, parallel data are transmitted through a parallel transmission line.

Interface system in copying system

Abstract: PURPOSE:To connect apparatus having interface circuits of different specifications by using an interface adaptor having a serial interface circuit and a paral lel interface circuit. CONSTITUTION:An interface adaptor 7 is interposed between a semiautomatic original feeding device (SADF)2 which can input and output only a parallel signal 3, and a high class machine 4 which can input and output only a serial signal 6. That is to say, the parallel signal 3 from the SADF2 is converted to the serial signal 6 by the interface adaptor 7, and the serial signal 6 from the high class machine 4 is converted to the parallel signal 3 by the interface adaptor 7. The adaptor 7 is constituted of a CPU10, an ROM11, an RAM12, a parallel I/O8 and a serial I/O9. In this way, by adding the adaptor of a simple constitution, an apparatus having different interface specifications can be connected, and the possibility of combination of a product is increased.

Interfacing Apple and IBM computers for the analysis of clinical biofeedback

Abstract: This paper demonstrates a method of transferring research data from a remote clinic to a large university mainframe for data manipulation and statistical analysis. Data collected by an Apple //e computer were transferred to an IBM 3031 mainframe by sending data files to an IBM PC by telephone modem or by direct hardwire connection to the PC. The IMB PC performed data-formatting routines and then uploaded the files to the mainframe for storage. Advantages and disadvantages of sending data over telephone lines via a modem are discussed.

Scale with processor controlled operations

Abstract: A computation and control module suitable for use in a variety of postal scales as well as other types of mailroom equipment is disclosed. The module includes a microprocessor (20) and associated circuitry; connectors (40, 50) for connecting ROM (42), which stores firm ware for controlling the microprocessor (20), and PROM (52), which store postal rate charts; an input/output connector (70); a serial interface (90) for communications with postage meters; a non-volatile memory (110) for storing parameters specific to particular units; and an auxiliary input/output connector (100). The auxiliary input/output connector is driven by selected, memory mapped interface circuitry mounted on the PROM card (52). The module also includes a load cell interface (120) and a power supply (30). In one embodiment, switches (95, 115, 125), responsive to the microprocessor, are provided for sequentially energizing various connectors and interfaces, so as to reduce power requirements. Systems comprising a plurality of computation and control modules are disclosed. Other systems including battery powered modules mechanically and electrically interconnected by a power distribution bus are also disclosed, as a modular power bus.

Serial interface control system

Abstract: PURPOSE:To reduce the load of a CPU by comparing the data sent from a data processor with the data obtained by a loopback on the basis of the designated mask information and reporting the result of comparison to the data processor. CONSTITUTION:A serial interface control circuit 1 receives a command (1) from a data processor 6 and turns off a control line 15 to set the loopback state within the circuit 1 as long as the command indicates the loopback. At the same time, the circuit 1 holds the mask information transferred by the command at a mask circuit 12. Then the circuit 1 receives a command (2) and compares the data transferred from the processor 6 with the data obtained from an input line 3 based on the sequential mask information. The command is finished correctly if the coincidence is obtained from the comparison at a time point when the transfer is through with data. While an abnormal end is decided if no coincidence is obtained from said comparison. Thus an executing action is discontinued. Here the command (1) refers to the execution for the transfer and the loop test of the mask information; while the command (2) refers to reporting an abnormal end.

Insertion System and digital data restitution using a time code binds a program recorded on VCR

Abstract: System and insertion of digital data restitution using a time code associated with an audiovisual program recorded on VCR. This system essentially includes nine functional blocks: a main memory 120, an address generator 124, two digital conversion circuits 126, 128, a serialization code circuit 130, a switching circuit 132, a circuit deserializing the videographic code 134, a serial interface circuit 136 and a control circuit 140. a bus 114 connects the blocks. Application television. (CF DRAWING IN BOPI)