Showing papers on "Serial port published in 1986"

Apparatus and associated methods for converting serial data pattern signals transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel pattern output signals

Abstract: A system is disclosed which includes methods and apparatus for transmitting asynchronous nonhomogeneous variable width parallel data pattern inputs in a format suitable for use with a synchronous high speed serial link. The system further includes means for receiving the serially transmitted data which is capable of reversing the process performed by the transmitter, i.e. the receiver is capable of outputting the nonhomogeneous variable width parallel data as originally input to the system. The receiver is further operative to identify output data by type. The disclosed means for transmitting and means for receiving are each cascadable. As a result the disclosed system permits a wide variety of parallel data patterns to be manipulated, transmitted and received sharing a single serial interface.

Microcomputer with a multi-channel serial port having a single port address

Abstract: A microcomputer having a dual-channel serial port is disclosed, where both channels of the serial port have the same addressable location. On the transmit side of the serial port, two data words are sequentially written to a two stage first-in first-out memory from the data bus of the microcomputer, when the serial port is addressed. At such time as a frame of data is to be transmitted, the framing signal causes the contents of the two stages of the first-in first-out memory to be loaded into separate transmit shift registers, for serial transmission from the pair of serial output terminals. On the receive side of the serial port, a pair of shift registers each receive serial data at the serial input terminals; at the end of the data frame, the contents of the shift registers are loaded into intermediate receive registers. The contents of the intermediate receive registers are multiplexed onto the data bus, responsive to a read instruction addressing the serial port. Encoding and decoding hardware is provided which allows the data to be selectively companded according to the micro-255 law or to the A law, both prior to transmission and after receipt.

System for transmitting and receiving asynchronous nonhomogeneous variable width parallel data over a synchronous high speed serial transmission media

Abstract: A system is disclosed which includes methods and apparatus for transmitting asynchronous nonhomogeneous variable width parallel data pattern inputs in a format suitable for use with a synchronous high speed serial link. The system further includes means for receiving the serially transmitted data which is capable of reversing the process performed by the transmitter, i.e. the receiver is capable of outputting the nonhomogeneous variable width parallel data as originally input to the system. The receiver is further operative to identify output data by type. The disclosed means for transmitting and means for receiving are each cascadable. As a result the disclosed system permits a wide variety of parallel data patterns to be manipulated, transmitted and received sharing a single serial interface.

Digital subscriber controller

Abstract: A digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two 64 kilobit-per-second voice/data channels and a 16 kilobit-per-second data control channel. Among the digital ports is a three-channel serial interface port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected. The controller includes a line interface unit, a data link controller which processes data channel information present at the line interface unit, a main audio processor, a microprocessor interface, and a multiplexer which establishes the data paths selected by the subscriber.

Programmable data-routing multiplexer

Abstract: A multiplexer for use in a digital subscriber controller having a number of analog ports and digital ports which can be programmed via an external microprocessor to establish time-division multiplexed bidirectional data paths between three subscriber-selected ports designated as "sources" and three subscriber-selected ports designated as "destinations". Among the ports is a line-interface port having two 64 kilobit-per-second channels on which analog/digital data is received from and transmitted onto the network transmission line. Among the digital ports is a three-channel serial port and a two-channel microprocessor interface port. An analog port is also provided at which a variety of audio transducers may be connected. The data-routing multiplexer consists of three sections, each comprising a plurality of registers connected to a single internal bus on which time-division-multiplexed signals are generated and received by particular subscriber-selected registers, each register within a section serving as either a generator or a receiver for the internal bus for a particular digital channel. An extension of the internal bus is connected to the analog port. A set of three control registers stores the subscriber-selected sources and destinations. Control signals are generated therefrom which affect the subscriber-selected interconnection of registers within the data-routing multiplexer with the internal bus. The multiplexer facilitates maintenance and testing of the digital subscriber controller by permitting a loopback path to be established for a device connected to a port by simply designating a path having that port as both its source and destination.

On-vihicle communication equipment

Abstract: PURPOSE: To remarkably reduce the number of wires in a cabin by providing a transmission medium connecting plural controllers by a serial date like and plural serial interfaces acting as a prescribed operation. CONSTITUTION: A serial interface M6 inputs a serial data sent from a corresponding controller M4 through an input terinal and sends the data to other controller M4 through a transmission medium M5 connected to the control terminal. Further, the serial data sent from other controller M4 via the transmission medium M5 is inputted through the connection terminal and the serial data are sent to the corresponding controller M4 via an output terminal. Since the plural controllers are subjected to serial data link in this way, the wiring up to a parameter detection means located at a remote position from each controller is not required and the number of wires in the car body is reduced remarkably. COPYRIGHT: (C)1987,JPO&Japio

Arrangement for the individual adaptation of a serial interface of a data processing system to a data transmission speed of a communication partner

Abstract: An arrangement, for adapting the serial interface of a data processing system to the data speed of a communication partner, has a recognition circuit for recognizing the transmission speed wherein signals from the communication partner having the unknown transmission speed are inputted to a frequency counter of the recognition circuit and the resulting count provided to a microprocessor which calculates an adjustment division signal N from the counting results. The adjustment divison signal N is inputted to a frequency divider of a phase lock loop (PLL) circuit of an adjustment circuit to provide a divided clock frequency signal which is compared with a divided reference frequency signal by the PPL circuit so that the frequency of a voltage control oscillator of the PLL circuit is adjusted until the divided clock frequency signal and divided reference frequency signal are equal. The adjusted voltage control oscillator signal is inputted to the microprocessor from which a matching data transmission speed equal to the data transmission speed of the communication partner is calculated.

Supervisory Control of Single Axis Controllers for Modular Robotic Systems Using a Serial Interface

Abstract: A microprocessor-based controller for a range of pneumatically-actuated, servo-controlled, single degree of freedom, modular robotic units is now available in commercial form. This product, known as a single axis controller (SAC), is the result of SERC sponsored collaborative work by the Department of Engineering Production at Loughborough University of Technology (LUT) and Martonair UK. To co-ordinate the activities of a number of these units a supervisory controller is required. Such supervisors may communicate with SACs via either a serial or a parallel interface. This paper describes the facilities available to a supervisory controller using the serial interface and provides an example of their use.

Serial data processor

Abstract: PURPOSE: To form a serial interface with small hardware without deteriorating the executing efficiency of an executing part, by applying the macroservice processing to perform transmission/reception of the serial data. CONSTITUTION: This serial data processor contains the memory parts 102 and 103 which store programs and various data, an executing part 101 which interprets the contents of programs and executes them, a status register 200 which stores the status information showing the executing state, and a serial interface part 400 which transmits and receives the serial data. The part 101 interrupts execution of a program while holding the status information showing the program executing state into the register 200 and transmits and receives the serial data by a serial data processing request signal received from the part 400. Then the part 101 restarts the program execution. The part 400 produces repetitively the processing request signals by the prescribed timing until the transmission and reception of data are through. Thus the serial data are intermittently processed. COPYRIGHT: (C)1988,JPO&Japio

A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

Abstract: A full-duplex transceiver chip incorporating an adaptive echo cancelling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer and a digital phase locked loop. The paper emphasizes system design considerations and a chip architecture minimizing power dissipation, silicon area and off-chip components. A double poly 3- \mu m CMOS technology is used to implement the 5-V 22-pin device which dissipates less that 50 mW and occupies 27.7 mm^2 .

System for controlling articulated robot

Abstract: A system for controlling articulated robot wherein a cycle which receives serial data from an external instruction device and a cycle which reversely converts the received serial data into correction data on each of the axes from orthogonal coordinates and distributes them, are executed in parallel by first and second operation units (CPU-a, CPU-b) in a robot control unit which is served with control target information on the articulated robot via a serial interface (11), in order to produce in real time a robot drive instruction that corresponds to said control target information maintaining a sufficiently short interpolation interval, and in order to control the operation of each of the axes.

Communication system between microprocessors

Abstract: PURPOSE:To perform transfer by using serial ports between microprocessors which differ in serial communication system by generating a clock signal with a serial transfer speed through the mutual synchronization of a counter between clock signals. CONSTITUTION:When data is set in the serial buffer 5 of the 1st microprocessor 1, a status signal (b) becomes busy and when the transmission of the data from the serial buffer 5 is completed and a stop bit SP is sent out, the status signal becomes ready. The sent data is applied to the serial input port SI and interruption port IRQ of the 2nd microprocessor 2, and when a start bit is detected, the counter is started and a clock signal CK 2 is applied to a serial clock port SC, so that received data is written in a serial buffer 6. The status signal (c) of the serial buffer 6 becomes full and the data is transferred to a logical processing part, etc.

A 160-kb/s digital subscriber loop transceiver with memory compensation echo canceller

Abstract: A full-duplex transceiver chip incorporating an adaptive echo canceling modem and a 2.048-Mb/s serial interface is described. The device provides a full-duplex communication link at 160 or 80 kb/s on up to 4 or 5 km, respectively, of 0.5-mm twisted-pair cable. Full integration is achieved through the use of RAM-based sign-algorithm echo-cancellation, biphase line code, a fixed switched-capacitor equalizer, and a digital phase locked loop. The authors emphasize system design considerations and a chip architecture minimizing power dissipation, silicon area, and off-chip components. A double poly 3-/spl mu/m CMOS technology is used to implement the 5-V 22-pin device which dissipates less than 50 mW and occupies 27.7 mm/SUP 2/.

Serial i/o system

Abstract: PURPOSE:To use a serial interface as a bus, by providing one control line in addition to serial I/O lines for multi-CPU system contained in a microprocessor. CONSTITUTION:A microprocessor 1 having a control function and microprocessors 2 and 3 using serial interfaces respectively perform designed functional processes and necessary data input/output through the serial interfaces. Serial I/O lines 4-7 which connect the microprocessors 1-3 with each other are provided and the serial I/O lines 4 and 5 are used as data input- output lines among the microprocessors 1-3. The serial I/O line 6 is used as a synchronizing clock line. The line 7 is made active by means of output signals of the microprocessors 2 and 3 and used as a control line for informing the microprocessor 1 having a control function of a control request for outputting serial data, when the microprocessors 2 and 3 want to output the serial data.

System for the insertion and reproduction of data using a time code linked to a programme recorded on a video tape

Abstract: This system essentially comprises 9 functional units: a central memory (120), an address generator (124), two digital conversion circuits (126, 128), a code-serialising circuit (130), a switching circuit (132), a circuit (134) for deserialising the videographic code, a serial interface circuit (136) and a management circuit (140). A bus (114) connects the units. Application to television.

Telephone transfer device of telephone set function incorporation type

Abstract: PURPOSE:To attain a sure and quick information transmission by transmitting the storage content of a storage device directly. CONSTITUTION:The main body 1 is provided with a transmitter 41 transmitting the content stored in a storage device 5, and the transmitter 41 is provided with a serial interface 42 converting a parallel digital signal from the storage device 5 into a serial digital signal, a modulator-demodulator 43 converting the digital signal into the analog signal and an amplifier 44. Since the serial interface 42 converts the parallel digital signal from the storage device 5 into the serial digital signal, the digital signal is converted into the analog signal by using the modulator-demodulator 43, and the signal is transmitted to the storage content of the storage device 5.

PC applications: Engineering: Only recently endowed with the power to do engineering chores, personal computers am already saving designers time and money

Abstract: The role of the personal computer in engineering and science laboratories, traditionally the realm of the most powerful state-of-the-art computers, is discussed This trend was started by the introduction of the IBM PC AT in the summer of 1984 The machine is based on the 16-bit Intel 80286 microprocessor, which is more than twice as powerful as the 8088 microprocessor in the IBM PC Engineers have also been using PCs for controlling and coordinating test of complex systems Here, up to a dozen laboratory instruments, such as signal generators, voltmeters, and oscilloscopes are connected to the computer through a general-purpose interface bus or an RS-232 serial port The computer applies test signals, collects data, and compares the results with either prestored values or data collected during previous trials

Central monitor and control system for high-purity gas producing device

Abstract: PURPOSE:To decrease the number of nationwide workers by monitoring collectively the states of the controllers for high-purity gas producing devices provided at various areas throughout a country. CONSTITUTION:The data on the pressure and temperature inside a fractionating tower, the production amount of product nitrogen gas, the feed amount of fluid nitrogen, etc. are sent to a signal transmission line 45a from various gauges set at a high-purity nitrogen gas producing device 42. These data are converted into analog electric signals and supplied to a computer 41 set at a working site. Then the data of the computer 41 are converted into digital signals by an A/D converter 45 and processed by a CPU 43. These digital signals are converted into serial signals by a serial interface 46 and applied to a MODEM 55 to be converted into transmittable AC signals by a communication circuit 52. These signals are sent to an exchange station 57 via a communication control circuit 56. Then the data are supplied to a MODEM 55a via a communication control circuit 56a to be demodulated to the serial signals and applied to a central monitor computer 53. These serial signals are converted into parallel signals by a serial interface 46a and processed by a CPU 43a. Then these processed parallel signals are displayed on a CRT device 51a and also stored in a floppy disk 52.

Synchronizing serial interface

Abstract: PURPOSE:To use software change for expansion and to connect one transmission/reception means and lots of transmission/reception means by assigning a bit identifying information destination and sender to a format. CONSTITUTION:Figure shows a signal format representing the assignment of a serial input signal 1 and a serial output signal 2 in the unit of bits. A caption 4 indicates a signal format of a serial output signal and a caption 5 shows a signal format of a serial input signal and the bit assignment of the same form is attained. A bit C/D in the serial output signal 4 is a bit identifying whether a 8-bit frame is a command signal or a data signal, bits ID2, ID1 and ID0 (in total 3 bits) indicate bits forming ID codes of a destination together with the bit C/D, and lots of units are connected to one set of serial interface by transmitting/receiving a command signal. Since the ID code has 3-bit in this system, the data is transmitted to 8 units.