Showing papers on "Serial port published in 1989"

Low power optical transceiver for portable computing devices

Abstract: Optical transceiver (22) for calculator-to-calculator or calculator-to-module communication The transceiver (22) includes an IR transmitter (24) and IR receiver (26) designed for use in the low power, low cost environment of calculators and portable computing devices The transceiver may be adapted to communicate with the CPU (central processing unit (14) of a calculator (90) directly or with that of a portable computing device via its serial port (43) Devices in which the optical transceiver may be incorporated include calculators, plugless modules, and books containing plugless modules Data such as mathematical formulas within the book may be stored in the associated module and transferred instantaneously and accurately to an adjacent calculator upon request by the calculator

Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto

Abstract: The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system. Static bus holding devices are connected to the memories on which I/O terminals are connected, and allow the microprocessor to interpret trinary logic states presented to the I/O port leads by external devices.

Circuit for interfacing a digital signal processor to a serial interface controller

Abstract: An interface circuit which connects a Digital-Signal-Processor (DSP) to a serial controller. The interface circuit includes a bi-directional multiplexer which converts the separate address and data busses of the DSP to the multiplexed data and address bus of the serial controller. A timing generator is included for keeping track of the number of clock cycles in the present access. A decoder connected to the timing generator decodes the number of clock cycles and generates the appropriate control signals to both the serial controller and the DSP.

Registered RAM array with parallel and serial interface

Abstract: A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.

Serial port interface to low-voltage low-power data module

Abstract: A signal interface to a low-cost portable electronic token data module, which can be used with a wide variety of computers, including a tremendous variety of personal and other computers, as long as the computer includes an interface to RS232 (or some comparable stardard). The token has a one-wire-bus interface, implemented in a battery-backed open-collector architecture, which provides a read/wire interface. The communication protocol expected by the token has been specified so that the token never sources current to the data line, but only sinks current. The communication protocol also includes time-domain relations which are referenced to a very crude time base in the token, and the system must preserve timing relations which will be satisfied by tokens in which the time base takes on any of the wide range of forseeable speeds. To interface to this protocol, the programmable capabilities of the standard UART chip in the computer's RS232 interface are exploited to provide adaptation to the time base requirements of the module. This is done by writing an entire byte of output from the UART, at a much higher baud rate than the module can be relied on to accept, to write a single bit of data into the module. The read-data line (RX) of the UART is tied back to the transmit-data line (TX) through a resistor, so that the UART will also always report a read of the same data byte being written, unless the token has turned on its pull-down transistor. An electrical network is used at the interface which (in effect) reverses the ground plane identification of the two leads, but which does provide the correct signal polarity to the token for signal discrimination in read mode.

Sub-modular development system for modular computer-based instruments

Abstract: An instrument module development system for a computer-based instrument system, which system includes a chassis with slots for receiving various instrument modules and a system bus with a conventional computer bus for conveying commands and data between a host computer and the instrument modules and with additional lines for conveying control signals and data between the various instrument modules, has a module housing for insertion into one of the chassis slots, a development board mounted therein, and a serial input/output (SI/O) board. The development board includes a conventional computer processor, ROM, and computer bus interface circuits all interconnected by an intramodule bus. Firmware in the development board ROM enables the module to communicate with the host computer through the system bus. User developed applications firmware in the development board ROM enables the processor to communicate with and control a user provided instrument board via the intramodule bus. The SI/O board is provided with a RAM, a ROM and a serial port accessible through the intramodule bus on the development board. A user operating a computer connected to the serial port downloads, tests and debugs an application routine in the SI/O board RAM. When the user has perfected the application routine, the user may burn the routine into a development board ROM and disconnect the SI/O board from the development board.

Interface for coupling audio and video equipment to computer

Abstract: A method and apparatus for encoding data to be transmitted through a RS-422 standard serial interface such that the encoded data approximates one of the Control-L, Control-S wired or Control-S infrared protocols used in some audio and video equipment. Each bit of a data byte to be transmitted to the audio/video equipment is converted into one or more expansion bytes and transmitted at a baud rate such that the encoded bits approximate the shape and size of a bit in the data format of the selected protocol. In the case of Control-L protocol, the receiving port of the RS-422 is coupled directly to the serial interface port of the controlled device while the transmitting port is coupled through a diode to the serial interface port of the controlled device. For Control-S wired protocol, the transmit port of the RS-422 is coupled by an uninterrupted wire to the serial interface port of the controlled device. In Control-S infrared protocol, the transmit port of the RS-422 is coupled to an infrared light emitting diode which translates the data output from the RS-422 into infrared signals which are picked up by an infrared receiver at the controlled device.

Power down circuit for low-power circuit with dual supply voltages

Abstract: An integrated circuit which provides a low-power RS232 interface (or other serial interface). The integrated circuit receives separate power supply inputs for its own logic and for driving the serial line. Even if one of the power supply inputs fails, protection circuitry clamps floating nodes in the logic elements, and thereby avoids excessive current drain which might otherwise occur.

A real time integrated environment for Motorola 680xx-based VME and FASTBUS modules

Abstract: The Software Components Group pSOS operating system kernel and pROBE debugger have been extended to support the Fermilab PAN-DA data acquisition system for a variety of Motorola 680xx-based VME and FASTBUS modules. These extensions include: a multitasking, reentrant implementation of Microtec C/Pascal; a serial port driver for terminal I/O and data transfer; a message reporting facility; and enhanced debugging tools. An overview of the system is given, and the run-time-library reentrancy and process context, the serial port driver, the SYS68K Message Reporter System subroutine package, and the enhanced debugging tools are discussed. >

Control for a rotating media storage system

Abstract: The present invention is directed to a control system for a rotating media storage device. The rotating media storage device includes a control board having a ROM to store a basic power up control program, one or more processing means for control of the storage device and communication between the storage device and the host computer and a read/write memory means such as a RAM. When the storage device is powered up, the basic code in ROM initializes the control system, activates the rotating storage media, and accesses a control code stored on the storage media. This permits changing and updating of the control program simply by writing to disk and transferring the new program into the RAM for execution. In addition, it is not necessary to power down the drive in order to change the control program. The control system of the present invention includes a dual processor architecture for distributed control of storage device operations. Communication between the processors is accomplished on a microwire utilizing a novel communications protocol which permits high speed processing of individual distributed functions and high speed communication between the processors. The present invention provides a serial port coupled to the processors and used to implement a test environment with a host computer. Emulation code can be downloaded to the storage device to the serial port and stored in the RAM memory.

Dynamic video randam access memory

Abstract: PURPOSE: To obtain a hardware required for changing video information by providing an architecture for bringing a vector to address designation, provided with a memory, an address designating means, and a control means connected to a data means, for changing the stored video information. CONSTITUTION: Information stored in a video RAM 10 is sent successively to a color map circuit 40, and displayed on a monitor 20. A serial port control part 60 controls a transfer of the information stored in the video RAM 10 to the color map circuit 40. In the case of changing this information, a suitable instruction is sent to an interface circuit 160 from a CPU, etc., and transmitted into a graphic hardware circuit 110. A random port control part 120 controls a change of the information stored in the video RAM 10. In such a way, an image on the color monitor 20 of the video RAM can be changed. COPYRIGHT: (C)1990,JPO&Japio

Factory system, communication adaptor and method of operating factory system

Abstract: PURPOSE: To control a peripheral equipment without providing a programmable logic controller by arranging a communication adapter equipped with a data processor for executing the translation of data transferred between a machine and a communication network and the control of the machine or the peripheral equipment between the machine and the communication network CONSTITUTION: This communication adapter 26 is constituted fasically of a transputer 28, and is provided with a media access computer 32 equipped with an inputting and outputting part for operating input and output through a link 30 to a network 10, and a memory ROM 40 for storing a program for operating the translation of the command and data of the network 10 and a command and data by a format peculiar to a specific machine with which the adapter is connected Also, the adapter 26 is provided with input and output ports 34, 36, 52, 54, and 56 The serial port 34 is connected through a serial link 31 with the machine, and the ports 52, 54, and 56 control the various kinds of means for executing an operation related with the connected machine, and/or receive signals from more than one probes combined with the machine or other sensors

Serial interface circuit

Abstract: PURPOSE:To realize the transmission/reception of the 2-bit data with a 1-cycle clock pulse and to attain the transfer of different data at one time up to two sets of devices between control systems by securing the input or output of serial data alternately at every bit between 1st and 2nd shift registers. CONSTITUTION:A serial interface circuit consists of a 1st shift register 5 which supplies the serial input data received from an input terminal 1 at every bit synchronously with the leading edge of a clock signal, an inverter 4 which inverts the clock signal, and a 2nd shift register 6 which supplies the serial input data at every bit synchronously with the leading edge of the clock signal inverted by the inverter 4. Both registers 5 and 6 shift out the stored parallel data at every bit synchronously with the leading and the trailing edges of the clock signal respectively. Thus it is possible to transmit/receive the 2-bit data with a 1-cycle clock pulse and also to transfer data simultaneously between two systems.

Information processor for connecting serial interface bus

Abstract: PURPOSE:To reduce the transmission delay of data as well as the load given to a relaying information processing part, by adding a data input/output terminal and a clock terminal to the master and slave information processing parts respectively and connecting these two terminals to a bidirectional serial data line and a clock signal line respectively so that data can be transferred directly between the slave information processing parts. CONSTITUTION:Then a slave information processor A transmits data to another information processing part, the transmitting part of the part A confirms whether a bidirectional serial data line is kept under a busy or non-busy state to turn the non- busy state into a busy state. Thus a clock signal transmitting circuit of a master information processing part transmits a clock signal to a clock signal line. The transmitting part of the part A sends a transmitter identification code to the bidirectional serial data line to show the transmitter synchronously with the clock signal received from the master information processing part. While a transmission control part of the part A compares the signal transmitted from the transmitting part with the signal received by the receiving part from the bidirectional serial data line. Then various control signals are sent to the transmitting part when the number of discordant bits exceeds a reference level.

Method for selecting interface for computer equipment

Abstract: PURPOSE:To eliminate the need for a specific selection key for selecting an interface and a monitor display device by deciding the depression of a data processing key allocated to an interface selecting key in initializing processing at the time of turning on a power supply. CONSTITUTION:Power is supplied from a power supply circuit at the time of turning on the power supply, and during the rise of the power supply, an outputted initializing signal is supplied and respective circuit elements are set to initial states. Then, a CPU 20 executes the initializing processing on the basis of a system program stored in a ROM 21. When a space key is depressed or the space key is depressed after inputting a key signal in the initializing process, a serial interface 28 is selected, and if the space key is not depressed, a parallel interface 26 is selected. Consequently, a specific key for selecting the interface can be omitted and the interface can be simply selected even by a computer equipment having no display device.

Data Communications Applications

Abstract: This chapter contains sections titled: A Full Duplex 1200/300 Bit/s Single-Chip CMOS Modem Line and Receiver Interface Circuit for High-Speed Voice-Band Modems A Single-Chip Frequency-Shift Keyed Modem Implemented Using Digital Signal Processing A CMOS Ethernet Serial Interface Chip A Single Chip NMOS Ethernet Controller A Monolithic Line Interface Circuit for T1 Terminals A 50-Mbit/s CMOS Optical Transmitter Integrated Circuit A 2Gb/s Silicon NMOS Laser Driver A 50Mb/s CMOS Optical Data Link Receiver Integrated Circuit Gigahertz Transresistance Amplifiers in Fine Line NMOS

A 27 MHz Programmable Module for VSP

Abstract: This paper describes a programmable logic module for the real-time processing of video signals. This module is part of a set of programmable modules, sharing a common communication strategy, that can be combined to realise an Integrated Circuit capable of handling complex video algorithms. The inputs to the module are first selected via a switch matrix and then stored in a two-port dynamic RAM to increase scheduling flexibility. Logic and Arithmetic operations are then performed using an ALU preceded by a set of barrel-shifters. A flexible instruction set is offered by the former, including data-dependent instructions. All sub-blocks are fully programmable using a central program-memory which is loaded via a serial interface. Extensive pipelining and an execution rate of one instruction per clock cycle contribute to a high processing throughput. Parameterized layout generators are used to facilitate ease of modification.

Method for testing remote supervisory and controlling equipment master station

Abstract: PURPOSE:To test the master station of a remote supervisory and controlling equipment by mutually connecting the line interface circuits of A and B both systems of a doubling constitution and when the master station or one side system is tested, operating the system of the other side in making it into a slave station simulator. CONSTITUTION:When an input, that the simulation of a second slave station is executed, is executed by the keyboard of a display 112, it is transmitted through a control circuit 122, a switching circuit 13 and a serial interface 5B4 to a main memory 2B by the control of a CPU 1B. According to a polling signal from a line interface 6A2 of the A system, the input is transmitted from a line interface 6B2 to the 6A2. The circuit 6A2 generates an interrupting signal to a CPU 1 at the time of a receiving completion, the CPU 1A rends the reception information ot the circuit 6A2, it is accumulated in a main memory 2A, it is outputted through circuits 5A1-5A3 to a system displaying panel 7, a printer 9 and a display 111, and while the a system executes the simulation of the second slave station, the A system of the master station can be tested. At the time of the test or the H system of the master station, the test can be executed in the same way by switching the switching circuit 13, and the test can be executed by only the master station.

Interface switching system

Abstract: PURPOSE:To allow the titled system to correspond to both start-stop asynchronous (ASYNC) and SDLC systems only by replacing chips to a microcontroller by applying common hardware and software to a means similar to transmission control procedure. CONSTITUTION:When a MCS 51 is applied as a microcontroller 1, its families are 8051 and 8044, a difference based upon ASYNC or SDLC is applied to a serial port and also a difference is applied to the fact that an internal RAM is divided into 128 bytes for the ASYNC and 192 bytes for SDLC. Pins other than a serial port pin are used in common and the ROM external versions for both the ASYNC and SDLC are 8031 (1b interface) and 8344 (1a interface). At the time of ASYNC, A is used for transmission data and B is used for receiving data, and at the time of SDLC, A is used for both transmission and reception and B is not used.

Control of an Experiment to Measure Acoustic Noise in the Space Shuttle

Abstract: : This thesis describes the potential use of a general-purpose controller autonomously to measure acoustic vibration in the Space Shuttle Cargo Bay during launch. The experimental package will be housed in a Shuttle Get Away Special (GAS) canister. We have implemented the control functions with software written largely in the c programming language. We use an IBM MS/DOS computer and C cross-compiler to generate Z-80 assembly language code, assemble and link this code, and then transfer it to EPRON for use in the experiment's controller. The software is written in a modular fashion to permit adapting it easily to other applications. The software combines the experimental control functions with a menu-driven, diagnostic subsystem to ensure that the software will operate in practice as it does in theory and under test. The experiment uses many peripheral devices controlled by the software described in this thesis. These devices include: a solid-state data recorder, a bubble memory storage module, a real-time clock, an RS-232C serial interface, a power control subsystem, a matched filter subsystem to detect activation of the Space Shuttle's auxiliary power units five minutes prior to launch, a launch detection subsystem based on vibrational and barometric sensors, analog-to-digital converters, and a heater subsystem. The matched filter design is discussed in detail in this thesis, and the results of a computer simulation of the performance of its most critical sub-circuit are presented. (jhd)

Process monitor control system

Abstract: PURPOSE:To monitor the plant state of all plant installations by a common portable monitor by connecting an interface of a portable monitor to an interface for data communication equipment provided with a process controller connected to each plant installation. CONSTITUTION:Plant installations P1-Pn are provided respectively with process controllers 5,5,... and a data communication equipment 6 is used between a process computer 2 and the process controllers 5,5,... and they are interconnected by a public line network 7. The state of the plant installations P1-Pn is monitored by displaying the information designated by the operator through the operator console 4 in a central monitor room 1 onto a CRT display device 3. In the individual monitor of the plant state in the plant installations P1-Pn at the site, the serial interface 12e of the portable monitor 12 is connected to the serial interface 5d for data communication of the process controller 5 of the object plant installation.

Microprocessor unit incorporating debugging device

Abstract: PURPOSE:To ensure an easy countermeasure even to the future improvement of a bus architecture owing to the high performance of an MPU by using a debugging-only serial port in addition to an MPU bus unit which performs the normal communication and obtaining an MPU containing a debugging circuit and a breaking circuit which are connected to said serial port. CONSTITUTION:A debugging circuit 113 receives a control command 101 and gives the direct write and read accesses to an internal register group 111 regardless of a bus unit 114 as long as the command 101 is equal to the write and read commands to the group 111. For the break of execution of a program, a breaking point is previously set at a breaking circuit 112 and the circuit 113 sets an MPU 110 under a program traveling state. When the program reaches the breaking point under such conditions, the circuit 112 stops the drive of the MPU 110. Thus it is possible to perform a debugging job by checking the contents of the group 111, a memory device 120 and an I/O device 130 respectively.

Serial interface circuit

Abstract: PURPOSE:To halve bit number of a shift register by detecting the transmission of bit number being a half the bit number of a serial data and transferring a data fetched in a latch circuit at the point of time to the shift register so as to send the serial data CONSTITUTION:Only a data in n-bit being a half of 2n-bit among the data in 2n-bit to be transferred is stored in a shift register 1, the remaining data in n-bit is stored once in latch circuits 3a-3d and transferred to the shift register 1 after the transfer operation of n-bit in the shift register 1 is finished That is, since the shift register 1 processes the data to be transferred by a half each, the number of stages by a half bit number has only to be prepared to a data length of the serial data Thus, the shift register 1 is constituted by a fewer number of stages than a conventional stage number, the hardware is reduced and the chip area is decreased

Interface for printer

Abstract: PURPOSE:To realize communication from a printer to a host computer, by providing a transmission means which outputs serial data synchronizing with a clock signal as one of output signal lines from the printer to the host computer CONSTITUTION:The setting of a serial interface mode is performed by a command outputted from the host computer 14 to the printer P An input/output interface 13 is set at a serial mode, and initial setting to receive the serial data from the printer P is performed The input/output interface 13, in case of inputting data, generates an interruption signal at a CPU1, and a serial interface mode setting command is stored in an input buffer 31 Meanwhile, the CPU1 of the printer P is started up and a signal SLCT is set at an L level, and a signal BUSY is set at an H level, then, the transmission of the serial data can be performed

The design of an integrated circuit for use in a smart RS-232 cable

Abstract: A smart RS-232 cable capable of automating the process of connecting two serial ports together has been designed. After making the physical connections, the user is required to input the baud rate and the port description: either listener or talker/listener. The custom-designed integrated circuit interrogates the ports and makes the logical connections of the TXD, RXD, DTR, RTS, CTS, DSR, DCD, and GND lines for transmission to take place. The design of the system has led to the development of an algorithm for interrogating RS-232 ports as well as a method for the interconnection of bidirectional signals where very little information about the other side is known. The design was performed on an Apollo 3000 workstation using the LIS (Laboratory for Integrated Systems) software, and the ASIC (application-specific integrated circuit) was designed for implementation in a 3- mu m double-level metal process. Full-chip-level simulation results verify the correct operation of the smart RS-232 connection. >

Intelligent direct-current voltameter

Abstract: The utility model discloses an intelligent direct-current voltameter which is used to measure direct current electric quantity, electric current, and voltage The intelligent direct-current voltameter comprises an 8-bit single chip microprocessor, a program memory, an analogue to digital converter, an I/O extension interface, an electronic multiway switch, a presetting channel amplifier, a displayer, a keyboard, a drive and control circuit, a serial interface, four color miniature printer The intelligent direct-current voltameter adopts an 8-bit single chip microprocessor to measure the accumulated value of the direct current electric quantity, and the 8-bit single chip microprocessor matches with an A/D conversion circuit to achieve a multiplex measuring The man-machine conversation and measurement parameter controlling are achieved by the keyboard The intelligent direct-current voltameter which can match with a printer to print and measure data adds an electronic clock to time for users, and the serial interface is left for standby

Portable data collector

Abstract: PURPOSE:To miniaturize the titled collector and to lighten the collector in weight, by allowing a tuning circuit which receives the serial transfer of a program and data in an asynchronous communication system by using an electromagnetic induction system to a data repeater to share with a tuning circuit to charge the secondary battery of the portable data collector from the data repeater by using the electromagnetic induction system. CONSTITUTION:The portable data collector tunes a signal electromagnetically inducted from the data repeater by the tuning circuit consisting of a coil 1 and a capacitor 2. The tuned signal is wave-formed by a diode 3 and a resistance 4. Then it charges the secondary battery 5 and simultaneously it is amplified and wave-formed by a gain amplifier. The program and the data are transferred between the portable data collector and the data repeater through a serial interface part in the asynchronous communication system. Therefore since one tuning circuit is used for the charging of the secondary battery and the program and the data transfer between the portable data collector and the data repeater, the portable data collector can be miniaturized and lightened in the weight.

Design and implementation of a user-friendly interface for DIII-D neutral beam automated operation

Abstract: The operational interface to the DIII-D neutral beam system consisted of several interactive devices that the operator used to sequence neutral beam conditioning and plasma heating shots. Combined with an ongoing effort to increase the degree of automated operation and its reliability, a single microcomputer-based interface for each of the four neutral beam MODCOMP Classic control computers was developed, effectively replacing some twenty pieces of hardware. Macintosh II microcomputers were selected, with 1 MB RAM and off-the-shelf input/output (I/O) consisting of a mouse, serial ports, and two monochrome high-resolution video monitors. The software is written in Pascal and adopts standard Macintosh window techniques. From the Macintosh interface to the MODCOMP Classic, the operator can control the power-supply setpoints, adjust ion source timing and synchronization, call up waveform displays on the Grinnell color display system, view the sequencing of procedures to ready a neutral beam shot, and add operator comments to an automated shot-logging system. The Macintosh interface also provides a springboard for increased levels of automation of the neutral beam control system, within the framework of a cost-effective and standardized software environment. >