Showing papers on "Serial port published in 1991"

Voice-actuated, speaker-dependent control system for hospital bed

Abstract: A voice-actuated environmental operator system of the kind which enables a user/patient to use simple voice commands to control a plurality of hospital environment room functions including operation of selected bed movement and room environment functions associated with a provided multi-function hospital bed. The operator system uses a conventional IBM PC, XT, AT or like computer which has been adapted for interfacing in a pass-through manner with the control unit of a provided hospital bed. The computer includes a voice card and associated voice recognition and training software for interpreting and translating voice input into digital information readable by a controller card for operating a plurality of bed motor and room function commands. The controller card includes a plurality of relay switch devices, each of which are dedicated to performing a specific bed movement or room function. An FCC registered data access arrangement is also provided to the controller card for telephone interface capability. In a first embodiment, data communication between the computer and the provided hospital bed's control unit is by pass-through hard wire cable interface connection between bed control unit and the DB9 and DB15 serial port connectors on the back of the computer. The DB9 and DB15 serial port connectors are desoddered off the computer's motherboard and wired directly to the controller board. A headset microphone assembly wearable by a patient user is provided to the system for transmitting voice input to said voice recognition means and receiving system command confirmation signals and telephone communications.

Data transfer system between a computer and a host adapter using multiple arrays

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation. Likewise, the computer accumulates data for the TTY devices and transfers this data to the adapter in one transfer operation. Communication between the adapters and concentrators through the high speed serial communication link is implemented using a small fixed-size addressed packet to achieve a low overhead, high performance communications protocol. Each high speed link between an adapter and a concentrator is implemented to provide inherent flow control of data. The concentrators include a fail safe global flow control mechanism to prevent overflow of data from the TTY devices.

Method and apparatus for remotely accessing a plurality of server consoles

Abstract: A method and apparatus providing remote access to server consoles in a network is disclosed. The method and apparatus provides remote access by utilizing a single server designated an access server, multiple serial port means attached to this single access server, and a plurality of additional servers coupled to this multiple serial port means. The method and apparatus couples the server console lines to the serial ports of the multiple serial port means as well as server console terminals. Remote access is accomplished by gaining access to the access server, which then provides access to any one of the serial ports associated with the access server, thereby providing remote access to any one of the plurality of server console lines coupled to the multiple serial port means. This capability is accomplished while local accessibility to the server console terminals is maintained.

Multi-port memory

Abstract: The multi-port memory of the present invention is provided with a random port for describing the graphic data, a first serial port for reading the data to be displayed, and a second serial port for writing the dynamic picture image data and which has a transfer mask register to transfer the dynamic picture image to a window. The multi-port memory enables multi-window display of the dynamic picture images in a simple circuit structure, with ensuring high-speed erasure and scroll of the multi-window.

Communication adaptor for game set

Abstract: A communication adapter which is used with a plurality of game sets for transmitting and receiving data related to the game states of the game sets. Each game set including a serial interface and a buffer memory for temporarily storing transmit/receive data. The adapter including: a housing; a connection terminal for each game set; data input, data output and clock output ports, a clock signal generator, format converter and transmit/receive storage means. The clock signal generating means applies the same clock signal used for data communication with the game sets to each clock output port so that data to be transmitted to each game set and data received from each game set is synchronized with the clock signal whereby reliable communication is obtained with two or more game sets without the use of modems.

Wearable system for acquisition, processing and storage of the signal from amperometric glucose sensors.

Abstract: A wearable device for the acquisition, processing and storage of the signal from needle-type glucose sensors has been designed and developed as part of a project aimed at developing a portable artificial pancreas The device is essential to assess the operational characteristics of miniaturized sensors in vivo It can be connected to sensors operating at a constant potential of 065 Volts, and generating currents in the order of 10(-9) Amp It is screened and equipped with filters that permit data recording and processing even in the presence of electrical noise It can operate with sensors with different characteristics (1-200 nA full scale) The device has been designed to be worn by patients, so its weight and size have been kept to a minimum (250 g; 85 x 145 x 35 cm) It is powered by rechargeable Ni/Cd batteries allowing continuous operation for 72 h The electronics consists of an analog card with operational amplifiers, and a digital one with a microprocessor (Intel 80C196, MCS-96 class, with internal 16-bit CPU supporting programs written in either C or Assembler language), a 32 Kb EPROM, and an 8 Kb RAM where the data are stored The microprocessor can run either at 5 or 10 Mhz and features on-chip peripherals: an analog/digital (A/D) converter, a serial port (used to transfer data to a Personal Computer at the end of the 72 h), input-output (I/O) units at high-speed, and two timers The device is programmed and prepared to operate by means of a second hand-held unit equipped with an LCD display and a 16-key numeric pad(ABSTRACT TRUNCATED AT 250 WORDS)

Nonvolatile serially programmable devices

Abstract: An integrated circuit including a serial interface (12) having a nonvolatile memory (30) coupled to a and configuration of circuit boards and entire systems. A configurable circuits (10) containing switches, resistors, capacitors or digital logic devices has an unique identification code and is electrically configured by connection to a nonvolatile memory (30). An interrogation shift register (38) and a configuration data shift register (36) are serially connected to receive a serial bit stream (50) containing an interrogation code section and a configuration data section. The interrogation code, which is identical to the identification code of a selected one of the configurable circuits, is compared with the circuit identification code to provide a match pulse (42) that enables a program signal to initiate transfer of data from the data shift register (36) to the nonvolatile memory (30).

Expandable communication system with automatic data concentrator detection

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation. Likewise, the computer accumulates data for the TTY devices and transfers this data to the adapter in one transfer operation. Communication between the adapters and concentrators through the high speed serial communication link is implemented using a small fixed-size addressed packet to achieve a low overhead, high performance communications protocol. Each high speed link between an adapter and a concentrator is implemented to provide inherent flow control of data. The concentrators include a fail safe global flow control mechanism to prevent overflow of data from the TTY devices.

Expandable communication system using data concentration

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation. Likewise, the computer accumulates data for the TTY devices and transfers this data to the adapter in one transfer operation. Communication between the adapters and concentrators through the high speed serial communication link is implemented using a small fixed-size addressed packet to achieve a low overhead, high performance communications protocol. Each high speed link between an adapter and a concentrator is implemented to provide inherent flow control of data. The concentrators include a fail safe global flow control mechanism to prevent overflow of data from the TTY devices.

Data concentration interface for configuration of multiple TTY devices

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Automatic alarm code converter

Abstract: An automatic alarm code converter wherein a plurality of alarm dialers report alarm conditions using security industry standard pulsed tone, FSK, or DTMF formats and call through the PSTN to the converter. The converter comprises a telephone line interface/decoder, a microprocessor which correlates the received alarm ID and code with addresses in a page data memory. The page data memory contains a pager number and an associated alphanumeric ASCII message The code converter further comprises a software program embodied in an EPROM which instructs on the automatic formatting of the page data into the PET/TAP protocol. The code converter communicates the page data to the paging system through a full duplex serial port either by direct RS232 connection or remotely through a dial-out modem using the PET/TAP protocol.

Video random access memory with fast, alligned clear and copy

Abstract: A video random access memory (VRAM) includes a dynamic random access memory (DRAM) array and a serial access memory (SAM) connected to bi-directional random and serial ports. The SAM provides the capability for partial but aligned data transfer or mask write back of data from an external source for subsequent partial write operations in the DRAM array. These sources include color registers, on-chip arithmetic logic unit (ALU) output, or the random port. Partial but aligned transfers from the SAM to the DRAM array are accomplished by a data transfer into a selected row between two specified column addresses of the DRAM array. Alternatively, a masked write back into a row of the DRAM array is based on mask register contents. Improved serial access memory data input operation for DRAM array is accomplished by means of a source of "0s" or "1s" for a clear operation, providing a page mode fill from the RAM port or an on-chip ALU, and providing a color register load or based on random port input data. In addition, the use of a mask register for partial write back into a row also enhances serial access memory data input operations to the DRAM array. In one modification, a second SAM connected to a second bi-directional serial port is provided. The second SAM is connected to the first SAM to transfer data therebetween in parallel.

SAM data selection on dual-ported DRAM devices

Abstract: The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

Video memory array having random and serial ports

Abstract: An architecture for a memory array having a random access port and a serial access port configured and operable to provide selectively different ordering of the data bits at the two ports. The invention finds particular application in frame buffer VRAMs where video display pixel data is functionally replicated in the cells of the memory array. The pixel data at the serial access port is structured to coincide by row with the raster scan of the video display. On the other hand, addressing through the random access port provides pixel data for multiple rows, preferably in 2 x 2 pixel blocks, to improve rasterization processing efficiency for pattern variations projecting orthogonal to the scan orientation. The architecture is accomplished through the judicious sharing of column select functions and shift register arrangements. The invention is amenable to a mode select so as to provide conventional operation whereby both the random and serial ports communicate with analogous pixel data bit orders.

Image displaying apparatus for reading and writing graphic data at substantially the same time

Abstract: An image displaying apparatus has a dual port memory with a plurality of memory fields. Picture data generated by an NTSC TV camera are sequentially inputted to the serial ports of the dual port memory and then read out via the serial ports to be transferred to a video monitor. Since the transfer of data between each serial port and the memory field associated therewith is effected in parallel, the transfer is performed during the blanking period of the video monitor. In a period other than the blanking period, display data are sequentially fed from one serial port to the video monitor, while video data are fed to the other serial port. During such an input/output period, graphic data generated by a graphic processor are randomly written to the memory via random ports. The graphic data and the picture data are stored in the memory fields to produce display data to be displayed on the video monitor.

Data transmission system for process automation control - uses full duplex transmission for data transfer using frequency shift keying modulation

Abstract: The data transmission system uses frequency shift keying modulation for transmission of measured values via a two-wire line. The central control has a central processor (6) supplying the required values for each remote device (2) coupled to the line (3) via a modem (4) and a capacitive coupling (5). The data received from the remote device via a capacitive coupling and the modem, with a corresp. modem (4) within each remote device (2), coupled via a serial interface to a microcontroller (7). Pref. the current for the electronic circuit (8) of each remote device is supplied via the same line, with a line adaption stage for extraction of the AC and DC signals. ADVANTAGE - Error-free transmission of monitored and control values.

Video educational device

Abstract: PURPOSE: To explain working facilities and equipment and to assist operation by projecting video information which is edited by the object facilities and equipment on a screen together with a speech output. CONSTITUTION: An operator carries a remote controller 61 and puts on a headphone set 62 connected thereto. A connector 60 is connected to the serial interface of the object facilities or equipment. A cassette 56 which is generated corresponding to the object facilities or equipment is loaded in VTR equipment 52. An IC card 54 as a video control information storage device is set on a projection processor 53. The projection processor 53 while inputting output information from the object facilities or equipment decides conditions and continues or temporarily stop projection operation or makes a jump to other video information. Explanatory images as to various educational items are projected on the screen 57 of a television set 51 and then line constitution, the respective specific items of the constitution of the equipment, a before-start inspecting method, a starting method can be known. COPYRIGHT: (C)1993,JPO&Japio

Data processing system

Abstract: PURPOSE:To execute the memory access at a high speed by using a serial port and a random port in the case of an instruction fetch and a data operation, respectively with respect to a memory access request from a processor CONSTITUTION:The system is constituted of a microprocessor 101, a read-only memory for holding a fundamental program, a dual port memory (DP-RAM) 103, a random port control circuit 104 for generating a control signal of a random port of the DP-RAM, a serial port control circuit 105 for generating a control signal serial port of the DP-RAM, a deciding circuit 106 for deciding by which of the random port and the serial port an access is executed, a peripheral processor 107 and a clock generator 108 In such a state, with respect to a memory access request from the processor 101, the serial port and the random port are used in the case of an instruction fetch and a data operation, respectively In such a way, the memory access can be executed at a high speed

Design Of A Parallel Bus-to-Scan Test Port Converter

Abstract: The IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture [1] as well as other scan path methodologies use a serial interface for transmitting data to and from the circuit under test. This serial communication presents an efficiency problem in transferring data between a processor and the scan ring. This paper describes the architecture and features of a device that interfaces a parallel host bus to a serial test bus. The Parallel/Serial (P/S) Converter integrates several features to simplify board test and offers a way to make scan operations more efficient by managing shift operations directly in hardware.

Diagnosing apparatus of breakdown for vehicle

Abstract: PURPOSE:To enable execution of a simple and easy operation by providing a detecting means of detecting a unit for control which can communicate with a tester and by providing the unit for control with a storage means of storing the result of detection by the detecting means. CONSTITUTION:A tester 1 is connected to ECU (engine control unit) 2 by a communication line 5 through the intermediary of a serial interface 3 and a concentrated connector 4 and delivers a diagnosis instruction. It can also receive various informations from the ECU 2 side and conducts mutual transmission and reception of informations with the ECU 2 by bidirectional serial communication. Besides, the ECU 2 is connected with a number of sensors 6 and actuators 7 disposed in various places of an engine and thereby various controls of the engine are executed. Moreover, the connector 4 is connected with control units 20 to 23 fitted to a vehicle, through the communication line 5. Since a table of the results of the previous inspection is stored in a nonvolatile memory 8, maintenance can be executed simply and conveniently by reading out the content of the memory 8 at the time of the maintenance.

Serial interface control system and method therefor.

Abstract: A plurality of serial ports (55, 56), a built-in modem slot (52), a propriety slot (51), and an industrial standard slot (53) are provided. Interrupt request levels of these serial ports, slots, and input/output base addresses, are set in a setup processing through a keyboard. Circuits (62, 63, 64, 65) are provided for disabling modem inserted in the buit-in modem slot when an optional modem is inserted in the propriety slot (51). Interrupt request levels from the serial port and from the slots and the interrupt level from the industrial standard slot are wire-ORed. When an industrial standard board is inserted in the industrial standard slot, the serial ports, the built-in modem slot, and the propriety slot are disabled.

Interface tester for different async. data communications systems - has various interface, and can detect and analyse errors

Abstract: An interface tester (1) in the form of a mobile unit has four mutually independent, real-time data channels (10-13), a memory for up to 7000 characters, an integrated time detector and a printer interface for a printer (6) or a parallel or serial interface and a terminal (8) interface. The tester has a serial interface to a host computer (7) and different modules, which can be mixed together, for connection of the data channels. USE/ADVANTAGE - For testing different asynchronous data communications systems. Tester has a low drop-out time and can detect and analyse errors.

Electronic controller for vehicle

Abstract: PURPOSE:To execute serial data communication between plural microcomputers in synchronism with the rotation of an engine by making a data transmitting means transmit data and a data receiving means receive them with some phase difference kept between the above actions. CONSTITUTION:At least the first microcomputer 11 of plural computers is provided with a transmitting port 12A, from which data are transmitted by one bit in fixed order according to the rotational angle of a crankshaft. The second microcomputer 21 is provided with a receiving port 22B connected to the transmitting port 12A, and the data are received by one bit according to the rotational angle of the crankshaft from the port 22B. In addition to that, data transmitting and receiving performed by the microcomputers 11 and 21 respectively are executed with some phase difference kept between them. Thus, data communication can be executed between the microcomputers in synchronism with the rotation of an engine without providing special serial ports.

Automatic payment system

Abstract: The invention can be used directly by the public as an autonomous system whereby standardized payments can be made. It includes a microcomputer 1 which has a communication plate 5 via which it is connected to: a printer 12 which incorporates a code reader 13, an internal keyboard 11 and a central computer 14, for reading the receipt, generating a duplicate of operations carried out and carrying out programming with the keyboard 11 or with the communication plate 5 via dispatch from the central computer 14. The microcomputer 12 includes a controller 4 which is connected to a colour monitor 10 for presentation and entry of data by the customer and operator. The microcomputer 1 includes a serial port (gate) which is connected to: a coin reader 8 and a banknote reader 7 for allowing payment. The microcomputer includes a parallel port 2 which is connected to a coin issuer 6 for dispensing change.

One-chip microcomputer

Abstract: PURPOSE:To eliminate the need for a reset detecting circuit by detecting a reset command signal in a serial signal from another one-chip microcomputer and performing initialization processing. CONSTITUTION:The one-chip microcomputer is constituted by adding a conventional one-chip microcomputer main body part 101, a reset control part 102, a serial interface part 103, a reset detection part 104 which detects the reset signal in the serial signal sent to the serial interface part 103, and a reset signal synthesis part 105 which synthesizes and outputs the reset command signal detected by the reset detection part 104 to the reset control part 102. The reset detection part 104 detects the reset command signal in the serial signal from another one-chip microcomputer and the reset control part 102 places the one- chip microcomputer main body part 101 in resetting operation according to the reset command signal detected by the reset detection part 104 to perform the initialization processing. Consequently, the reset detecting circuit is not necessary.

Serial access memory device capable of controlling order of access to memory cell areas

Abstract: A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.

Computing system having apparatus for conducting serial port extended buffering exploitation using a protocol overide mechanism.

Abstract: There is disclosed a method of conducting input/output of data in a serial manner. The input/output of data is controlled by a buffering controlled processor at the I/O port. In accordance with the method, the control buffering of the I/O of data is overridden to determine if a connected peripheral has greater buffering capabilities than that of the I/O port processor. If so, the override is maintained.