Showing papers on "Serial port published in 1997"

Method and apparatus for configuring a camera through external means

Abstract: A camera (10) having a built-in microprocessor for accepting configuration data from an external device (14). The camera (10) has a serial port (16), and a slot (18) for receiving standard type II and III PCMCIA cards (22) for data input and output. These features provide the camera (10) with the capability of being programmed by an external device (14), including downloading configuration data including a particular operating system, custom modules, graphics and textual data, and data base information and operational parameters. The configuration data can also be downloaded from one camera (10) to another camera (12).

Debug interface including operating system access of a serial/parallel debug port

Abstract: A debug interface supports data transfer using read and write system calls that communicate data without stopping an executing kernel. The printf( ) command passes an information string to an executing operating system. The information string summons the operating system to use a serial debug port to signal to a debug device, such as a host system, that is connected to the serial port. The debug interface-supported read and write operations and system calls allow the kernel and executing applications software, respectively, to continue executing during the read and write data transfers. The debug interface includes support for a plurality of extended function sideband signals that extend the functionality of the read and write functionality to allow the processor to concurrently run kernel and application programs while transferring data using read and write operation. The extended function sideband signals include a command acknowledge signal (CMDACK), a dual-purpose break execution and trace control signal (BRTC), an execution stopped and receive data signal (STOPTX), and an off-chip trigger event signal (TRIG). The debug interface further includes a buffer for transferred data The kernel may run a first data transfer command which is not fully transmitted when a second data transfer command is issued. The operating system supports buffering of the data evoked by the second data transfer command using a conventional queuing operation.

A Personal Dead Reckoning Module

Abstract: Point Research Corporation of Santa Ana, CA has developed a new lightweight miniature Dead Reckoning Module (DRM) for drift-free navigation by personnel on foot. The traditional compass and pace-count dead reckoning navigation has been replaced by a continuous hands-free module. An internal solid-state 3 dimensional compass provides a robust tilt-corrected heading. We automate step counting with an electronic pedometer. The pager-sized module also includes a barometric altimeter. The module reports data, and is controlled via bi-directional RS-232 serial interface. A second serial port on the module may be connected to a GPS receiver. When GPS is available, the module will blend the data with DR using a Kalman filter. It provides a seamless navigation solution through many buildings, in canyons, or other areas where the GPS signal is compromised. The DRM is protected under U.S. patent number 5,583,776.

System for displaying system status

Abstract: A fault tolerant computer system for obtaining and displaying, or updating the status of server components through a remote interface and either a local or remote client machine without intervention of the server operating system software. The remote machine accesses the server by use of a dial-in modem connection, while the local machine accesses the server by a local serial connection. The components that can be monitored include, but are not limited to, the following: Power Supplies, Temperatures, Fans, Processors, I/O Groups, I/O Canisters, Serial Numbers, and Revisions.

System for resetting a server

Abstract: A fault tolerant computer system for resetting a server through either a local or remote client machine. The remote machine accesses the server by use of a dial-in modem connection, while the local machine accesses the server by a local serial connection. The resetting operation brings the server and operating system software to a normal operational state. Reset is used after diagnostics or recovery have been performed without the use of the server operating system software or to restart the server after an unexpected crash.

Processor including a combined parallel debug and trace port and a serial port

Abstract: A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

DSP based dynamic resource allocation multiprocessor communications board

Abstract: DSP based dynamic resource allocation multiprocessor communications boards may be used in either a circuit-switched data system or a packet switched data system including a plurality of channels for transmitting bit streams including service data packets and corresponding call setup requests indicative of a required amount of digital signal processing for the corresponding service data packets. For use in the circuit-switched data system, a dual port memory pool is partitioned into a plurality of memory sections each partitioned into memory portions including an input portion and an output portion. Each memory portion is accessible via first port and a second port. A distributing function unit provides multiplexed/demultiplexed paths between the channels and the memory sections. A processing bank includes a plurality of digital signal processors selectively connectable in series via serial ports to selectively operate in a plurality of modes including pipeline modes. A resource controller is coupled to the distributing function unit and to the processing bank. The controller implements resource control functions for dynamically allocating resources of the processing bank based on the required amounts of digital signal processing indicated by the call setup requests. The controller provides control signals to the processing bank to select at least one processor for processing tasks related to each call setup request and to selectively enable the serial ports to selectively provide pipeline processing between the processors.

Dynamically allocating space in RAM shared between multiple USB endpoints and USB host

Abstract: The present invention relates to a peripheral microcontroller for providing a high performance USB (Universal Serial Bus) connection to existing peripheral architectures (such as printers and disk drives with existing microcontrollers) and to new peripheral architectures (such as a 4-port USB-to-Ethernet Bridge). The USB peripheral microcontroller includes three units. A Serial Interface Engine (SIE) connects to a USB host or USB hub. A Microcontroller (MCU) Interface Unit connects to one or more peripheral devices such as ISA-like peripherals. A Memory Management Unit (MMU) provides a buffering mechanism between the SIE and MCU Interface Unit. The MMU utilizes a unique data packet buffering architecture. Packets received at the MMU from a peripheral for transmission to the USB host and packets received at the MMU from the USB host for transmission to a peripheral are buffered in a RAM. The capacity of the RAM is dynamically allocatable among various USB endpoints and the USB host so that the size of the RAM is minimized. The data path of the inventive USB peripheral controller is also highly advantageous. The SIE accesses the packet buffer RAM via a DMA controller in the MMU. The MCU Interface Unit accesses the packet buffer RAM via a microcontroller or a DMA controller. An arbiter in the MMU enables these multiple masters to access the packet buffer RAM.

Computer controlled security and surveillance system

Abstract: The present invention provides a complete, easy to use and install security and surveillance system for a personal computer, which is designed to act as a peripheral to the personal computer. The system utilizes a radio frequency device having receiving and transmitting means connected between the serial port of the personal computer and various sensors to input signals to the non-data pins of the serial port whereby software in the personal computer interprets the signals received at the non-data pins to place a call to a pager or cellular phone, or communicate with another computer, produce sound effects, and/or operate video equipment.

Method of displaying system status

Abstract: A fault tolerant method of obtaining and displaying, or updating the status of server components through a Remote Interface Board and either a local or remote client machine without intervention of the server operating system software. The remote machine accesses the server by use of a dial-in modem connection, while the local machine accesses the server by a local serial connection. The components that can be monitored include, but are not limited to, the following: Power Supplies, Temperatures, Fans, Processors, I/O Groups, I/O Canisters, Serial Numbers, and Revisions.

Serial-port powered caller identification computer interface

Abstract: A computer interface device for answering calls on a telephone line and transmitting a ring signal and caller identification information to the computer. The interface device is powered by the computer's serial port. The interface device operates in one of two modes of operation. In the call receive mode, the device answers calls and transmits caller identification and ring information to the computer. In the dial mode, the computer places calls on the telephone line. The computer controls activation of the interface device's operational modes.

Image pickup device

Abstract: PROBLEM TO BE SOLVED: To provide an image pickup device that can transmit a video signal from an image pickup means using a few signal lines, without deteriorating the S/N in analog way SOLUTION: A pre-processing circuit 10b applies correlation duplex sampling to a video signal from an image pickup element 10a of an image pickup circuit 10, an automatic gain control 10c amplifies the processed video signal to have a required amplitude, a one-bit modulation circuit 11 samples the amplified signal to convert the signal into one-bit serial data, adds a device number to identify the image pickup element, a valid line number and a line number or the like to the serial data, and a serial interface 13 converts the data into a differential signal and an optical signal and transmits the converted signal to a signal processing section A serial interface 14 of the signal processing section receives the serial data, a one-bit demodulation circuit 15 eliminates the device number, the line number and the valid line number, and a signal processing circuit 16 applies down-sampling to the one-bit data to convent the data into a PCM signal and to provide the output of the PCM signal

Method of resetting a server

Abstract: A fault tolerant method of resetting a server through either a local or remote client machine. The remote machine accesses the server by use of a dial-in modem connection, while the local machine accesses the server by a local serial connection. The resetting operation brings the server and the operating system software to a normal operational state. Reset is used after diagnostics or recovery have been performed without the use of the server operating system software or to restart the server after an unexpected crash.

Method of powering up or powering down a server to a maintenance state

Abstract: A fault tolerant method of powering up and powering down a server through either a local or remote client machine. The remote machine accesses the server by use of a dial-in modem connection, while the local machine accesses the server by a local serial connection. The power up operation brings the server to a maintenance state such that diagnostics or recovery can be performed even though the server operating system software is not operational. Power down is used when certain types of diagnostic, maintenance, or administrative tasks need to be done.

System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted

Abstract: A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits. Each ASP is configurable to generate an ASP interrupt request signal when the value of the last of the multiple data bits is equal to a predetermined value, preferably when the last data bit is set to 1 as commonly used to signal the beginning or end of a data packet. Each ASP includes at least one configuration register, the contents of which determine the operation of the ASP. Generation of the ASP interrupt request signal and the internal DMA request signal is determined by the contents of at least one bit position within the configuration register.

Mixed-mode multi-protocol serial interface driver

Abstract: A mixed-mode multi-protocol serial interface driver is presented. The driver operates in current-mode, voltage-mode, or both, and includes circuitry for conforming output signals to one of a plurality of selectable electrical interface standards, including, for example, CCITT/EIA standards V.35, V.11/RS-422, V.28/RS-232, and V.10/RS-423. A mode-select input signal selects a particular standard, and appropriate portions of the circuitry are enabled in response. Portions of the circuitry not enabled are placed in a high impedance state to prevent their interference with the enabled portions.

Generic serial interface with automatic reconfigurability

Abstract: A generic serial interface includes any one of multiple transition cables having a first connector conforming to one of several different serial interface standards. A second generic connector is connected to a second end of the transition cables. A configurable interface circuit is coupled to the generic connector and is automatically reconfigured according to the physical interface type associated with the transition cable. The interface circuit includes a termination resistor array that can connect different termination resistor values to the same generic signals on the generic connector according to the interface type. The termination resistor array in combination with a unique designation of generic signals allow a single interface to operate with many different serial interface standards both in DCE and DTE modes while requiring substantially fewer connector pins and simpler interface circuitry than existing generic interfaces.

Serial port switching circuit for selectively connecting two serial ports to two serial communication connectors in response to a control signal

Abstract: A serial port switching circuit includes an input/output controller contained in a computer system, the input/output controller including first and second serial ports for performing serial data communication with external equipment, first and second connectors connected to the external equipment, and a switching arrangement connected between the first and second serial ports of the input/output controller and the first and second connectors, for selectively connecting the first and second serial ports to the first and second connectors in response to a control signal being applied according to a user's selection to allow the input/output controller to perform the serial data communication with the external equipment. According to the present invention, the user can simply switch the connections between the first and second serial ports of the input/output controller and the first and second connectors.

System for sending data from-and-to a computer monitor using a high speed serial line

Abstract: An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact. The computer system may include the remote transceiver for transmitting a return serial data stream, a transmitter operably coupled between the feedback input port and the remote serial output port, and a timing generator coupled to recover a clock signal from the serial data stream and to synchronize the deserialized data. The base transceiver may also include a serial input port for receiving the return serial data stream, a receiver operably coupled to the serial input port, and a return high speed serial connection between the remote serial output port and the base serial input port. The return serial data stream is received concurrent with the serial data stream being received.

Autonomous radio telemetry

Abstract: An improved radio modem is disclosed for use with an autonomous radio telemetry system. The radio modem includes a reprogrammable microprocessor, a radio transceiver, and a serial interface. By providing a software program within the radio modem that converts the serial interface into a general purpose interface to external input/output devices, and by providing additional programmed decision making capability into the radio modem, no external telemetry computer is required to interface with the input/output devices, and the radio modem operates as a combination telemetry computer and radio device. The radio modem also includes a novel reprogrammable state machine architecture for communicating with the input/output devices, and for deciding what actions to take based on the status of the external devices.

Computer interface architecture having a power saving function

Abstract: An information processing apparatus such as a personal computer is capable of controlling consumption power of a digital communication line interface circuit or a modem depending on a usage state of the communication line. In one aspect, the information processing apparatus including a digital communication interface circuit connected to a digital line to communicate data, includes a link state detect circuit to ascertain a link state between the interface circuit and the communication line, and a consumption power mode change circuit to change a consumption power mode of the interface circuit depending on the link state ascertained by the detect circuit. In one aspect, a battery-driven hand-held information processing apparatus minimizing the consumption power includes an access detection circuit to monitor an access state of software to a serial interface circuit, a timer circuit to determine that a modem is not accessed for a fixed period of time, a power control circuit to turn power of a modem circuit on and off in accordance with a result from the timer circuit, a circuit to generate a signal which masks a transmission enable signal notifying the serial interface circuit that the modem is unavailable because power of the modem circuit is off, and a mask circuit operating in response to the mask signal.

Apparatus and method for serial data communication utilizing general microcomputer

Abstract: An apparatus and method for serial data communication capable of performing an inter integrated circuit (I 2 C) serial data communication utilizing a general microcomputer having no built-in hardware for the I 2 C serial communication. In the apparatus, a start condition for a start of serial data transmission or reception is detected by a start condition detecting section utilizing an input serial clock signal and serial data of an I 2 C communication type, and a stop condition for a stop of the serial data transmission or reception is detected by a stop condition detecting section utilizing the serial clock and serial data. A microcomputer generates and releases an interrupt for the serial data transmission or reception in accordance with start and stop signals provided from the start and stop condition detecting sections, respectively, and then performs transmission or reception of the serial clock signal and serial data when the interrupt is generated.

Serial port interface system and method for an analog-to-digital converter

Abstract: A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration). An invalid command lock mode is also disclosed that places the serial port interface in a hold state, if an invalid command is decoded, to protect on-chip registers from corruption. Control of the serial port interface is removed from an external device until a specific restart sequence is applied.

Video projector controller

Abstract: PROBLEM TO BE SOLVED: To obtain the video projector controller for a multi-vision with simple configuration and without much adjustment time. SOLUTION: Each of plural projectors 2 (2a-2d) incorporates a control circuit 8 and a serial interface means 7. The controller 5 gives a control signal to the control circuits 8 (8a-8d) of the video projectors 2 to adjust or control the video projectors 2. Data communication terminal cables 3, 6 interconnect the controller 5 and one arbitrary video projector, and this video projector and the other plural video projectors in series via each serial interface means 7.

Moving reference channel quality monitor for read channels

Abstract: The present invention provides a method and apparatus for monitoring a read channel in a disk drive system and calibrating the disk drive system. In one embodiment, a comparator circuit is provided to detect the data samples, that fall within a pre-programmed, variable-width distribution window. The output of the comparator circuit is digitized and sent to a logic block to qualify the valid samples. A relative counter or histogram of the detected data samples is obtained. The valid sample count is fed to a counter that can be accessed via a serial port. The channel parameters can be adjusted based upon a relative figure of merit read off the serial port that reflects the distribution of the samples with respect to the target value after processing a statistically valid number of samples. An embodiment of the invention provides a slicer circuit which generates an ideal waveform that tracks the input signal. The ideal waveform constitutes a moving reference for comparison with the sampled signal in a channel quality monitor. The moving reference signal reduces hardware requirements in the comparing circuitry of the channel quality monitor. Further, hardware utility is optimized in an embodiment by driving an AGC tuning loop, an LMS filter tuning loop, and a channel quality monitor circuit from the same slicer circuit.

Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

Abstract: A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.

A method and system for reducing the pin count required for the interconnections of controller devices and physical devices in a network

Abstract: The present invention comprises a system and method for reducing the pin count between a plurality of MAC and PHY devices within a switching element. In this embodiment, the switching element includes a plurality of general serial interfaces for providing connections between respective MAC and PHY devices and each of the plurality of general serial interfaces operates at a first data rate. The system and method comprises a multiplexer coupled to the plurality of general serial interfaces and a pad member including a plurality of pins. The pad member is coupled to the multiplexer and receives multiplexed signals from the plurality of general serial interfaces. The multiplexer operates at a second data rate that is a multiple of the first data rate. Generally, a system and method in accordance with the present invention allows for the multiplexing of a general purpose serial interface (GPSI) to reduce the pin count in some cases by as much as 75 % and also synchronize the MAC/PHY interface. In this example, the multiplexer interface uses a total of 7 pins and supports a total of four MAC/PHY connections. If only GPSIs were utilized, 28 pins would be required for this function. The same multiplexing technique will also reduce the MAC/PHY interface in four 100Mbps connections from 56 pins for a four port system to 18 pins. In each example the multiplexer interface will operate at four times the speed of the general serial interface.

Serial interface circuit

Abstract: PROBLEM TO BE SOLVED: To provide a circuit for enabling smooth transmission/reception by dividing data to be transferred into data more than one, calculating the leading address of the next packet by adding a transfer data component from a leading bus address, generating the transmission packet of bus address addition at least and sending it to a serial interface when transferring the data of a present node to the other node. SOLUTION: A request packet generating circuit 122 divides computer data recorded through a transport data interface circuit 121 onto a hard disk into data more than one so as to be divided into packets in the case of write when the instruction of data transfer start from a control register 107 of a link layer circuit 100, and the address of an SBP protocol is calculated based on data such as the length of data set to the control register 107, and stored in a FIFO 124 for request. In the case of reception, the address of the SBP protocol is calculated. COPYRIGHT: (C)1999,JPO

Intelligent subsystem interface for modular hardware system

Abstract: A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Linking computers and consumer electronics

Abstract: The capabilities of our personal computers have increased dramatically over the past 15 years, and so has the number of connectors on the back of our systems. Originally, we needed a serial port for a modem and a parallel port for a printer. Now we also need ports for a mouse, audio input, audio output, video input, video output, Ethernet, and a camera. Enter the IEEE 1394 standard known as Firewire. This standard proposes to provide a single port on the back of our computers that can handle nearly all of the communication for which we now need eight to 10 ports. Along with connecting standard peripherals to computers, Firewire is designed for use with consumer audio, video, and television equipment.