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Showing papers on "Serial port published in 2001"


Patent
14 Feb 2001
TL;DR: In this article, a network configuration file is generated at a host computer and downloaded to a digital camera, which contains instruction information for communicating with a selected destination via a communications interface.
Abstract: A network configuration file is generated at a host computer and downloaded to a digital camera. This file contains instruction information for communicating with a selected destination via a communications interface. The digital camera includes a “send” button or LCD icon which allows the user to easily transmit one or more images via a wired or wireless communications interface to a desired destination, which among other possibilities may be an Internet Service Provider or a digital photofinishing center. When the user selects this option, the communications port settings, user account specifics, and destination connection commands are read from the network configuration file on the removable memory card. Examples of these settings include serial port baud rate, parity, and stop bits, as well as account name and password.

150 citations


Patent
29 Jun 2001
TL;DR: In this paper, an access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices, and a state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.
Abstract: An access detector detects an access type of an access to one of a plurality of serial ports interfacing to serial storage devices. The access is intended to one of a plurality of parallel channels interfacing to parallel storage devices via task file registers of the parallel channels. A mapping circuit maps the serial ports to the parallel channels. A state machine emulates a response from the one of the parallel channels based on the access type and the mapped serial ports.

53 citations


Patent
08 May 2001
TL;DR: In this article, a meshed backplane has dedicated pairs of connections for high-speed serial connection in each direction between each of multiple application modules and each other application module and a management/control bus is provided for out-of-band signaling.
Abstract: A meshed backplane has dedicated pairs of connections for high-speed serial connection in each direction between each of multiple application modules and each other application module. A management/control bus is provided for out-of-band signaling. The mesh of serial differential pairs may be used for management/control bus signals when necessary. A time division multiplexing fabric is also provided for telephony applications. A star interconnection region is provided for distribution of signals from redundant clocks.

53 citations


Patent
14 Mar 2001
TL;DR: In this article, the authors proposed a compact computing device with integrated network controller, integrated serial interface, on-board flash memory for nonvolatile storage, integrated random access memory for temporary calculations and software execution, integrated single-chip processor, and method for controlling aforementioned components, loading, updating, and executing software that performs a plurality of telecommunication applications.
Abstract: A compact computing device with integrated network controller, integrated serial interface, on-board flash memory for non-volatile storage, integrated random access memory for temporary calculations and software execution, integrated single-chip processor, and method for controlling aforementioned components, loading, updating, and executing software that performs a plurality of telecommunication applications, such as the collection, buffering, encryption, and transmission of call record data collected from a private branch exchange telephone switch over a secure, encrypted communication medium, and the management, control, and monitoring over a secure, encrypted communication medium of telecommunication devices such as a private branch exchange telephone switch, a voice mail system, and other associated telecommunication systems. The device provides the ability to remotely configure, control, monitor, and update said telecommunication systems from anywhere in the world via the Internet. The programmable device can also provide the mechanism to perform Web based Application hosting. Specifically, a telecommunications management program can be provided to customers as a hosted service which relieves the need to perform costly installation and performance tuning that for large systems can exceed by several times the actual cost of the purchased software. Users can access the telecommunications program through standard web browsers and perform all normal functionality such as running reports, directory services, billing, etc

46 citations


Patent
Reza Tanha1
10 Dec 2001
TL;DR: In this article, a dual interface serial bus that can support either the I2C or SPI interfaces is presented, without the use of an additional interface selectionpin (see Section 2.1).
Abstract: An electronic device (400) includes a dual interface serial bus that can support either the I2C or SPI serial interfaces. The device (400) defaults using the I2C serial interface for the transmission and reception of data. However, when the CE line (406) transitions from a logic high to a logic low state, the device (400) automatically reprograms the I/O to support the SPI interface standard. Both interfaces are supported without the use of an additional interface selection pin (308).

45 citations


Patent
09 Feb 2001
TL;DR: A bus emulation apparatus includes serial transfer paths, serial interface circuits having a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplying to a serial transfer path as mentioned in this paper.
Abstract: A bus emulation apparatus includes serial transfer paths, serial interface circuits having a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplying to a serial transfer path and a serial to parallel conversion circuit for converting serial data from a hub circuit to parallel data and supplying to a peripheral circuit, a hub circuit for supplying serial data from a serial interface circuit to a serial interface circuit connected to a peripheral circuit as a transfer destination of said parallel data among the serial interface circuits, and a network for connecting them, and installed on an LSI or a print circuit board to replaced a parallel bus.

36 citations


Patent
03 Dec 2001
TL;DR: In this paper, a time distortion circuit and a selector are interposed between the receiver and the transmitter for testing the serial port, where the selector selects between a receiver and a direct input, which provides an algorithmic test signal.
Abstract: An instrument for economically yet thoroughly testing serial ports employs a receiver and a transmitter. The receiver can be coupled to a TX line of a serial port for receiving a serial bit stream. The transmitter can be coupled to an RX line of the serial port for generating a serial bit stream. The receiver is coupled to the transmitter for establishing a loopback connection between the TX and RX lines of the serial port. A time distortion circuit and a selector are interposed between the receiver and the transmitter. The time distortion circuit adds predetermined amounts of timing distortion for testing the serial port. The selector selects between the receiver and a direct input, which provides an algorithmic test signal. The algorithmic test signal differs from the input serial bit stream received by the receiver to allow the TX and RX lines to be independently tested.

31 citations


Patent
Syed Faaiz Enam1, Masoud Djafari1, Duke Tran1, R. Smythe1, Michael Choi1, Bo-Shiou Ke1, Vi Lee1 
04 Jun 2001
TL;DR: Low frequency data loop-back as mentioned in this paper uses a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loopback test command.
Abstract: The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.

28 citations


Patent
06 Apr 2001
TL;DR: A protocol converter for use on board an aircraft with space limitations which converts navigation data from one format to another format for use by the aircraft's moving map display is described in this paper, where navigation data is supplied by an aircraft inertial navigation unit to the protocol converter in the ARINC-429 protocol which converts the data to the NMEA-0183 protocol.
Abstract: A protocol converter for use on board an aircraft with space limitations which converts navigation data from one format to another format for use by the aircraft's moving map display. The navigation data is supplied by an aircraft inertial navigation unit to the protocol converter in the ARINC-429 protocol which converts the data to the NMEA-0183 protocol. The converted data is then supplied to a moving map display on board the aircraft. An interface board receives ARINC navigational data from the aircraft navigation unit and stores the data prior to its transfer to a digital computer. The computer reads the data stored in the interface board including a status word which indicates the validity of the data. A computer software program within the computer converts the ARINC-429 navigational data to NMEA-0183 protocol data. The NMEA-0183 protocol data is transmitted through an RS-232 serial port to the moving map display.

26 citations


Patent
07 Feb 2001
TL;DR: In this paper, the authors propose a setting device for LAN printer equipment which makes it easy to set the environment structure of the radio LAN printer, can shorten the setting operation time, and is convenient.
Abstract: PROBLEM TO BE SOLVED: To provide a setting device for LAN printer equipment which makes it easy to set the environment structure of the radio LAN printer equipment, can shorten the setting operation time, and is convenient. SOLUTION: This device is connected to a printer device 10 mounted with the radio LAN printer equipment 15 through an interface cable 9 composed of a serial interface cable or parallel interface cable and is equipped with a control means 2 having an information analyzing means 3 which controls the output of request information and setting change information or setting information to the radio LAN printer equipment 15 and controls the display of setting information from the radio LAN printer equipment 15 and an information converting means 4 which converts the request information and setting change information or setting information, and can automatically set the radio LAN printer equipment 15 according to an operation style by sending the setting information to the radio LAN printer equipment 15 through the parallel interface cable 9 or serial interface able 9. COPYRIGHT: (C)2002,JPO

19 citations


Patent
25 Jul 2001
TL;DR: In this article, the authors present a circuit, apparatus, method, and signal set for sending and controlling bi-directional data flow between a microprocessor and a peripheral device having a standard UART-based, SPI-based or similar interface over a single input/output (I/O) port line, utilizing the differences of the instantaneous source impedance of the I/O port line operating with data in and data out states.
Abstract: Circuit, apparatus, method, and signal set for sending and controlling bi-directional data flow between a microprocessor (or other device) and a peripheral device having a standard UART-based, SPI-based, or similar interface over a single input/output (I/O) port line, utilizing the differences of the instantaneous source impedance of the I/O port line operating with data in and data out states. Circuit, apparatus, method, and signal set for separating the 1-wire data into standard 2-wire and 3-wire UART-based, SPI-based, or similar interfaces for use with unmodified peripheral devices. The exchange of data on a bit-by-bit or analog basis, with insignificant return delay, allows operation independent of any signaling protocol.

Patent
25 May 2001
TL;DR: In this article, the authors proposed a flexible UTOPIA-LVDS bridge device that transparently transports the full-duplex parallel bus over a high speed LVDS serial link.
Abstract: An UTOPIA-LVDS Bridge is a flexible UTOPIA to LVDS Bridge device. The LVDS Bridge transparently transports the UTOPIA bus over a high speed LVDS serial link. The device includes many reliability features such as an optional 1:1 protection and built in bit error rate checking. A parallel interface is user programmable for maximum flexibility. The user can choose between UTOPIA Level 2 ATM Layer (master) or PHY Layer 14 (slave) operation. The UTOPIA-LVDS Bridge supports a special MPHY (multi-PHY Layer 14 ) operation mode. The MPHY operation supports up to 248 standard UTOPIA Level 2 PHY ports without adding external circuitry. The serial interface uses LVDS Serializer and Deserializer technology. The 16:1 bit serialization allows conveying the full-duplex parallel bus over two differential transmission pairs. Bus LVDS technology also enables multi-drop configurations for distributing the UTOPIA bus to multiple Bridge receivers.

Patent
25 May 2001
TL;DR: The Utopia-to-LVDS bridge as discussed by the authors is a flexible Utopia to LVDS bridge device that transparently transports the UTOPIA bus over a high speed LVDS serial link.
Abstract: An UTOPIA-LVDS Bridge is a flexible Utopia to LVDS Bridge device. The LVDS Bridge transparently transports the UTOPIA bus over a high speed LVDS serial link. The device includes many reliability features such as an optional 1:1 protection and built in bit error rate checking. A parallel interface is user programmable for maximum flexibility. The user can choose between UTOPIA Level 2 ATM Layer (master) or PHY Layer 14 (slave) operation. The UTOPIA-LVDS Bridge supports a special MPHY (multi-PHY Layer 14 ) operation mode. The MPHY operation supports up to 248 standard UTOPIA Level 2 PHY ports without adding external circuitry. The serial interface uses LVDS Serializer and Deserializer technology. The 16:1 bit serialization allows conveying the full-duplex parallel bus over two differential transmission pairs. Bus LVDS technology also enables multi-drop configurations for distributing the UTOPIA bus to multiple Bridge receivers.

Patent
22 Feb 2001
TL;DR: In this paper, the authors present a system for remotely managing a network through serial ports, which consists of managed systems ( 110, 120 ) including a keyboard port and a monitor port, and a serial port having at least a transmission terminal and a reception terminal, the keyboard port having a higher priority than the serial port.
Abstract: Disclosed is a system for remotely managing a network through serial ports. The system comprises managed systems ( 110, 120 ) including a keyboard port and a monitor port, and a serial port having at least a transmission terminal and a reception terminal, the keyboard port and the monitor port having a higher priority than the serial port; a LAN ( 150 ) for enabling access to the managed systems ( 110, 120 ); a host box ( 100 ) including a switch realized through a single movable contact point connected to the LAN ( 150 ) and a plurality of fixed contact points connected to the managed systems; a keybox ( 118 ) interposed between the managed systems ( 110, 120 ) and the host box ( 100 ), the keybox ( 118 ) selectively outputting signals transmitted from the host box ( 100 ) to the output terminal of the keyboard port of the managed systems and to the serial port of the managed systems in accordance with the connection of a keyboard ( 114 ) and a monitor ( 116 ) respectively to the keyboard port and the monitor port; and a remote management server ( 160 ) connected to the LAN ( 150 ) via the Internet ( 40 ), the remote management server ( 160 ) performing the management of the managed systems through the host box ( 100 ).

Patent
11 Jan 2001
TL;DR: In this article, a method and apparatus for performing parallel asynchronous testing of a plurality of optical modules utilizes state machines that may be implemented in a common controller, which determines if a testing process or instrument required for the selected optical tests is available.
Abstract: A method and apparatus for performing parallel asynchronous testing of a plurality of optical modules utilizes state machines that may be implemented in a common controller. Desired optical tests are selected by an operator. The invention determines if a testing process or instrument required for the selected optical tests is available. A COM port may also be locked for each of the selected optical tests from among a plurality of COM ports to prevent interference between different tests. By reserving resources such as COM ports and testing instruments in this fashion the invention may asynchronously initiate execution of the selected optical tests. If a resource such as a COM port, testing process or instrument is not currently available, the test is place in COM port and testing queues to await availability of that resource. Once a test is completed, the resource is unlocked so that one of the state machines may asynchronously initiate another test. Various displays are generated so that an operator may view the progress of each of the tests. A database is utilized to store test results as well as test recipes and test instrument drivers that aid in the control of a testing architecture.

Patent
09 Feb 2001
TL;DR: In this article, a system and method for extending a separation distance between a PC and its accompanying keyboard, video display, mouse and serial port, which includes an internal expansion card disposed in a PC where the expansion card combines/multiplexes conventional keyboards, video displays, mice and serial signals, is presented.
Abstract: A system and method for extending a separation distance between a PC and its accompanying keyboard, video display, mouse and serial port, which includes an internal expansion card disposed in a PC where the expansion card combines/multiplexes conventional keyboard, video display, mouse and serial signals, to/from a combined signal on a single elongated link cable extending to a remote module disposed near the remote keyboard, video display, mouse and ports.

Patent
19 Dec 2001
TL;DR: In this paper, an order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bits (LSB) or from LSB to MSB.
Abstract: An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bit (LSB) or from LSB to MSB. Therefore, when the first device is used with a second device, integrated circuit (IC) or logic, which can handle the serial data in only one order, the first device is programmed, or configured, to handle the serial data in the same order as the second device.

Patent
30 Oct 2001
TL;DR: In this article, a dual serial port data acquisition interface assembly including a printed circuit board for supporting additional components of the dual-serial port assembly, a personal computer peripheral component interconnect connector secured to the printed circuit boards, and a serial-to-parallel converter to the personal computer is presented.
Abstract: A dual serial port data acquisition interface assembly including a printed circuit board for supporting additional components of the dual serial port assembly, a personal computer peripheral component interconnect connector secured to the printed circuit board for passing data between the printed circuit board and a personal computer. A first serial port connector mounted on the printed circuit transferring communication data and synchronization data between the personal computer and the data storage device through a programmed universal asynchronous receiver/transmitter microchip, and a second serial port connector mounted on the printed circuit board passing a performance data of the servo control circuit from the data storage device through a serial-to-parallel converter to the personal computer.

Patent
20 Feb 2001
TL;DR: In this paper, arbitration software operating on a computer is able to determine whether communication software utilizes the same serial communication (COM) port of the computer as a HotSync Manager, if its running, thereby enabling the serial COM port to be utilized for other purposes.
Abstract: Within one embodiment of the present invention, arbitration software operating on a computer is able to determine whether communication software utilizes the same serial communication (COM) port of the computer as a HotSync Manager. If they do use the same serial COM port, the present embodiment arbitration software shuts down the HotSync Manager, if its running, thereby enabling the serial COM port to be utilized for other purposes (e.g., wireless modem communication). However, if the present embodiment arbitration software detects a HotSync Request received via the serial COM port, it runs the HotSync Manager enabling a HotSync process to occur between (for example) a personal digital assistant (PDA) and the computer. Once the present embodiment arbitration software detects the completion of the HotSync process, it shuts down the HotSync Manager until it detects the next HotSync Request.

Patent
31 May 2001
TL;DR: In this paper, the authors present an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant.
Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit The UART chip also houses a data-storage-register circuit adapted to output status data to the parallel data bus, the status data being indicative of states of at least one of the serial communication circuit and the parallel bus interface circuit The arrangement of integrated circuit devices further includes a clock control circuit adapted to reduce the first clock rate in response to a clock control signal By reducing the first clock rate, the UART chip is configured to operate in a power-reduced mode while the serial communication circuit concurrently communicates serial data at the second rate

Patent
05 Jun 2001
TL;DR: In this article, a system and a method for health care through mobile communication network and/or internet are provided to measure number of walking and heartbeat of a user simultaneously and successively, supply various personal health information service in realtime and manage personal health by periods.
Abstract: PURPOSE: A system and a method for health care through mobile communication network and/or internet are provided to measure number of walking and heartbeat of a user simultaneously and successively, supply various personal health information service in realtime and manage personal health by periods. CONSTITUTION: A sensing device(103) comprises a vibration sensor part for sensing user's walking, a low frequency reception part sensing heart palpitation of the user, an input terminals, a recording medium, a serial port, a parallel port and a microprocessor part to sensing walking number and heart palpitation. A mobile communication terminal(104) connected to the serial and the parallel port of the sensing device(103) comprises a serial port, a parallel port, a microprocessor part, a receiving part, a transmitting part, a duplexor and an antenna to receive data signal of the number of walking and heartbeat and transmit the data signal to a mobile communication base station. A user's computer(102) has a web browser. A health care service system(200) comprises an operator web server(201) having connection through internet to the user's computer(102) and comprising a health care program accessing a data storage device(203) to supply necessary information to the user or receive information from the user and a data base server(204) to store the data in the data storage device(203). An information data signal transmitted from the mobile communication terminal(104) is passed through the mobile communication network and the data base server(204) and stored in the data storage device(103).

Patent
31 Jul 2001
TL;DR: By distributing the intelligence of a drive between a control unit and one or more intelligent power sections by using a high-power standardized serial interface for connecting these components, it is possible as a result to identify different power components with their performance data, and also to diagnose them.
Abstract: By distributing the intelligence of a drive between a control unit and one or more intelligent power sections by using a high-power standardized serial interface for connecting these components, it is possible as a result to identify different power components with their performance data, and also to diagnose them. Furthermore, independent innovations of the components are possible without having corresponding effects on the other components.

Patent
Ono Kazuya1
11 Oct 2001
TL;DR: In this article, a serial communication device bridging between a parallel bus and a serial bus, including a check bit producer which applies an error correcting code to parallel data transmitted through the parallel bus, a parallel-serial converter which converts the parallel data output from the check-bit producer, into serial data, and an error detector which checks an error-correcting code applied to the serial data.
Abstract: A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the parallel bus, (b) a parallel-serial converter which converts the parallel data output from the check bit producer, into serial data, (c) a serial-parallel converter which converts serial data transmitted through the serial bus, into parallel data, and (d) an error detector which checks an error correcting code applied to the serial data, and detects an error in the error correcting code.

Patent
13 Jul 2001
TL;DR: A programmable serial interface device (PSI) as mentioned in this paper is a programmable logic device and another die mounted to an assembly apparatus that converts between a first serial data signal and a first parallel data signal.
Abstract: A programmable serial interface device. The device generally comprises a programmable logic device and another die mounted to an assembly apparatus. The programmable logic device may comprise (i) a plurality of logic block clusters and (ii) a plurality of routing channels configured to interconnect said logic block clusters. The die may comprise a first communication channel (i) configured to convert between a first serial data signal and a first parallel data signal and (ii) coupled to a first of the routing channels to exchange the first parallel data signal with at least one of the logic block clusters.

Patent
23 Mar 2001
TL;DR: In this paper, a remote control system for a portable computer with a built-in IR receiver receiving IR signals emitted from a remote controller, comprising chipsets connecting the central processing unit to the IR receiver and to a serial port, is presented.
Abstract: A remote control system for a portable computer with a built-in IR receiver receiving IR signals emitted from a remote controller, comprising chipsets connecting the central processing unit to the IR receiver and to a serial port; a circuit switcheably connecting the IR receiver to the serial port; and software for determining whether to switch short the circuit by transmitting a first signal to the circuit and whether to switch open the circuit by transmitting a second signal to the circuit. The IR receiver is connected to the central processing unit through a FIR port; the first signal represents a switch from digit 0 to digit 1 of a particular pin of the circuit, while the second signal represents a switch from digit 1 to digit 0 of the same pin of the circuit; CIR signals received by the IR receiver are further transmitted to and received by the central processing unit through the serial port when the software switches short the circuit connecting the IR receiver to the serial port by transmitting the first signal to the circuit. Accordingly, the present invention allows the computer to receive, and thereby to be remotely controlled by, two differently encoded IR remote control signals, namely, FIR and CIR, with only one IR receiver.

Proceedings ArticleDOI
14 Aug 2001
TL;DR: This paper presents a simple technique in combining analog circuit and digital circuit theory together with programming technique to control the hardware for remote sensing of temperature and relative humidity.
Abstract: This paper presents a simple technique in combining analog circuit and digital circuit theory together with programming technique to control the hardware for remote sensing of temperature and relative humidity. The sensor circuit converts the relative humidity and temperature into an analog signal, which will then be applied, to a micro controller based data logger for storage purpose. The data is then transferred to the computer through RS232 standard serial port. The user interface program will be handling the data transfer between data logger and the computer as well as allowing the user to input some of the important parameters such as sampling interval and starting date and time for the logging operation. The system can perform in both real time and off line.

Patent
27 Apr 2001
TL;DR: In this article, an image display device has a serial port as data input and output port for the system, and a data processing virtual element for processing data inputs and outputs virtually as if the data input/output ports are connected directly.
Abstract: An image display device has a serial port as data input and output port for the system, and input and output data converting element for mutually converting the data format of input and output data for wireless communication. A data processing device has input and output processing virtual element for processing data input and output virtually as if the data input and output port are connected directly. The input data of the serial port is converted by the input and output converting element, and is transmitted to the data processing device through a wireless unit, and is processed through the input and output processing virtual element. The output data of the data processing device is transmitted to the image display device in the wireless unit by way of the input and output processing virtual element, and is converted by the input and output data converting element, and is issued to the serial port. At this time, depending on whether the serial port is being used or not, the control level of power saving operation is changed. In this configuration, the input and output peripheral device can be used at the display side, and power saving control in harmony between display function and input and output peripheral device function is realized.

Patent
25 May 2001
TL;DR: In this article, the authors proposed a flexible UTOPIA-LVDS bridge device that transparently transports the full-duplex parallel bus over a high speed LVDS serial link.
Abstract: An UTOPIA-LVDS Bridge is a flexible UTOPIA to LVDS Bridge device. The LVDS Bridge transparently transports the UTOPIA bus over a high speed LVDS serial link. The device includes many reliability features such as an optional 1:1 protection and built in bit error rate checking. A parallel interface is user programmable for maximum flexibility. The user can choose between UTOPIA Level 2 ATM Layer (master) or PHY Layer 14 (slave) operation. The UTOPIA-LVDS Bridge supports a special MPHY (multi-PHY Layer 14 ) operation mode. The MPHY operation supports up to 248 standard UTOPIA Level 2 PHY ports without adding external circuitry. The serial interface uses LVDS Serializer and Deserializer technology. The 16:1 bit serialization allows conveying the full-duplex parallel bus over two differential transmission pairs. Bus LVDS technology also enables multi-drop configurations for distributing the UTOPIA bus to multiple Bridge receivers.

Patent
13 Apr 2001
TL;DR: In this paper, a system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing is presented, where the physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time.
Abstract: A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.

Journal ArticleDOI
TL;DR: A simple and didactic experiment, used to control the temperature of an equipment, is described, using the use of two computers connected by serial ports and allowing students to build the controller and to disturb the process.
Abstract: Microcomputers introduced process control to a new era. A simple and didactic experiment, used to control the temperature of an equipment, is described. Features of this experiment include the use of two computers connected by serial ports and allowing students to build the controller and to disturb the process. © 2001 John Wiley & Sons, Inc. Comput Appl Eng Educ 9: 101–104, 2001