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Serial port

About: Serial port is a research topic. Over the lifetime, 12486 publications have been published within this topic receiving 51886 citations.


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Patent
24 Jun 1996
TL;DR: In this article, the authors describe a high speed data exchange between the peripheral devices for streaming continuous audio or video data in a vehicle computer, where the data stream is organized into multiple frames, with each frame having multiple data bits and at least one valid bit to indicate whether the data bits are valid.
Abstract: A vehicle computer system has a housing sized to be mounted in a vehicle dashboard or other appropriate location. The housing includes a base unit and a faceplate. A first logic unit is mounted to the base unit to form a support module. The support module has two interfacing slots and can support connections to multiple peripheral devices. The support module facilitates high speed data exchange between the peripheral devices for streaming continuous audio or video data. The support module has a fast data memory to temporarily hold data being communicated between the peripheral devices. The support module also has a memory access circuit associated with each of the peripheral devices which designates at least one storage area within the fast data memory to hold data received from, or to be sent to, the associated peripheral device. The vehicle computer has a computer module which can be connected to or removed from one interfacing slot of the support module. A multi-bit bus (e.g., PCI bus) interfaces the computer module and the support module. The vehicle computer system also has a logic unit mounted to the faceplate to form a faceplate module. This module is detachably connected to the other interfacing slot of the support module. When the faceplate module is attached, a high speed serial interface electronically couples the support module to the faceplate module. The high speed serial interface enables the logic units on the support and faceplate modules to exchange a high speed, synchronized, serial bit stream. This data stream is organized into multiple frames, with each frame having multiple data bits and at least one valid bit to indicate whether the data bits are valid.

122 citations

Patent
27 Dec 1995
TL;DR: In this paper, a RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity is presented, where control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs).
Abstract: A RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent device. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.

119 citations

Patent
05 Feb 1987
TL;DR: In this article, a triaxial accelerometer or other suitable sensor produces signals which are sampled by a microprocessor operating according to a program stored in a read-only memory.
Abstract: An apparatus for measuring and recording accelerations or other physical quantities experienced by easily damaged items of commerce such as fruit and electronic computers. A triaxial accelerometer or other suitable sensor produces signals which are sampled by a microprocessor operating according to a program stored in a read-only memory. When the sampled accelerations or other physical quantities exceed a predetermined threshold, samples are stored in a random access memory, along with their times of occurrence. The apparatus provides a serial port for reading out the recorded acceleration data. The data may then be subjected to further processing externally.

119 citations

Patent
03 Oct 1991
TL;DR: In this article, a high speed serial link between an adapter and a data concentrator is implemented to provide inherent flow control of data, and fail safe global flow control mechanism to prevent overflow of data from the TTY devices.
Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation. Likewise, the computer accumulates data for the TTY devices and transfers this data to the adapter in one transfer operation. Communication between the adapters and concentrators through the high speed serial communication link is implemented using a small fixed-size addressed packet to achieve a low overhead, high performance communications protocol. Each high speed link between an adapter and a concentrator is implemented to provide inherent flow control of data. The concentrators include a fail safe global flow control mechanism to prevent overflow of data from the TTY devices.

116 citations

Patent
05 Jan 2000
TL;DR: In this paper, a PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of video/audio encoder boards, each configured to receive and compress a corresponding video and audio stream.
Abstract: A PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of video/audio encoder boards, each configured to receive and compress a corresponding video/audio stream. The stat-mux board performs statistical multiplexing on the different compressed bitstreams to transmit multiple bitstreams over individual shared communication channels. Although each of the boards is configured to the system bus, each encoder board has a digital signal processor (DSP) with a synchronized serial interface (SSI) output port that is directly connected to an SSI input port on a DSP on the stat-mux board (which, in one embodiment, has four such DSPs each with six such SSI input ports). As such, (up to 24) compressed video/audio bitstreams generated on the various encoder boards can be transmitted directly to the stat-mux board without having to go through the system bus. In this way, the computer system can provide statistical multiplexing of low-latency video/audio bitstreams without having to suffer the processing delays associated with conventional transmission over PCI system buses.

113 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202231
202164
2020322
2019610
2018842