Topic

# Settling time

About: Settling time is a research topic. Over the lifetime, 4078 publications have been published within this topic receiving 36771 citations.

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TL;DR: The proposed self-tuning technique is applied to both PI- and PD-type FLCs to conduct simulation analysis for a wide range of different linear and nonlinear second-order processes including a marginally stable system where even the well known Ziegler-Nichols tuned conventional PI or PID controllers fail to provide an acceptable performance due to excessively large overshoot.

Abstract: Proposes a simple but robust model independent self-tuning scheme for fuzzy logic controllers (FLCs). Here, the output scaling factor (SF) is adjusted online by fuzzy rules according to the current trend of the controlled process. The rule-base for tuning the output SF is defined on error (e) and change of error (/spl Delta/e) of the controlled variable using the most natural and unbiased membership functions (MFs). The proposed self-tuning technique is applied to both PI- and PD-type FLCs to conduct simulation analysis for a wide range of different linear and nonlinear second-order processes including a marginally stable system where even the well known Ziegler-Nichols tuned conventional PI or PID controllers fail to provide an acceptable performance due to excessively large overshoot. Performances of the proposed self-tuning FLCs are compared with those of their corresponding conventional FLCs in terms of several performance measures such as peak overshoot, settling time, rise time, integral absolute error and integral-of-time-multiplied absolute error, in addition to the responses due to step set-point change and load disturbance and, in each case, the proposed scheme shows a remarkably improved performance over its conventional counterpart.

553 citations

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17 Nov 1993TL;DR: In this paper, the authors proposed a method of improving the utility of electrochemical glucose sensors by decreasing either or both their settling time and their sensitivity to interfering compounds, by pretreating the operating electrode with a negative electric current at a constant current density.

Abstract: A method of improving the utility of electrochemical glucose sensors by decreasing either or both their settling time and their sensitivity to interfering compounds. In particular, the settling time of an electrochemical glucose sensor is improved by pretreating the operating electrode with a negative electric current at a constant current density. The sensor's sensitivity to intefering compounds is reduced by operating the sensor at a reduced voltage while the glucose concentration measurement is being made.

432 citations

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TL;DR: In this article, the authors presented controller parameters tuning of differential evolution (DE) algorithm and its application to Load Frequency Control (LFC) of a multi-source power system having different sources of power generation like thermal, hydro and gas power plants.

320 citations

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TL;DR: In this article, the effects of pole zero pairs (doublets) on the frequency response and settling time of operational amplifiers were explored using analytical techniques and computer simulation, and it was shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time.

Abstract: The effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are explored using analytical techniques and computer simulation. It is shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time. The importance of doublet spacing and frequency are examined. It is shown that settling time always improves as doublet spacing is reduced whereas the effect of doublet frequency is different for 0.1 and 0.01 percent error bands. Finally it is shown that simple analytical formulas can be used to estimate the influence of frequency doublets on amplifier settling time.

300 citations

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18 Mar 2010TL;DR: This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation and achieves 100MS/s while consuming only 1.13mW.

Abstract: In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]–[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical 10b 100MS/s ADC, when the sampling settling time, comparator active time and SAR logic delay are subtracted from each period, the DAC settling time has to be less than 0.4ns in each bit cycle. Such a short time interval is not sufficient for the capacitive DAC to stabilize because the increasing interconnect line impedance in advanced processes slows down the charge transfer, especially in the longest routing path of the DAC capacitor network. Furthermore, the reference voltage sinks noise and line coupling also affects the settling. A non-binary SAR can tolerate DAC settling error at the cost of increased design complexity and hardware overhead [1]. This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. The ADC achieves 100MS/s while consuming only 1.13mW.

295 citations