scispace - formally typeset
Search or ask a question
Topic

Shift register

About: Shift register is a research topic. Over the lifetime, 16032 publications have been published within this topic receiving 125683 citations.


Papers
More filters
Patent
20 Jun 1986
TL;DR: Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
Abstract: A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.

1,116 citations

Journal ArticleDOI
X. Llopart1, M. Campbell1, R. Dinapoli1, D. San Segundo, E. Pernigotti2 
04 Nov 2001
TL;DR: The Medipix2 as discussed by the authors is a pixel-detector readout chip consisting of 256 /spl times/ 256 identical elements, each working in single photon counting mode for positive or negative input charge signals.
Abstract: The Medipix2 chip is a pixel-detector readout chip consisting of 256 /spl times/ 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. Each pixel cell contains around 500 transistors and occupies a total surface area of 55 /spl mu/m /spl times/ 55 /spl mu/m. A 20-/spl mu/m wide octagonal opening connects the detector and the preamplifier input via bump bonding. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to create a pulse if the preamplifier output falls within a defined energy window. These digital pulses are then counted with a 13-b pseudorandom counter. The counter logic, based in a shift register, also behaves as the input-output register for the pixel. Each cell also has an 8-b configuration register which allows masking, test-enabling and 3-b individual threshold adjust for each discriminator. The chip can be configured in serial mode and readout either serially or in parallel. The chip is designed and manufactured in a 6-metal 0.25-/spl mu/m CMOS technology. First measurements show an electronic pixel noise of 140 e~ root mean square (rms) and an unadjusted threshold variation around 360 e~ rms.

757 citations

Patent
23 Apr 1998
TL;DR: In this paper, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading.
Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

615 citations

Journal ArticleDOI
14 Jun 2002-Science
TL;DR: An all-metallic submicrometer device is demonstrated experimentally at room temperature that performs logical NOT operations on magnetic logic signals.
Abstract: An all-metallic submicrometer device is demonstrated experimentally at room temperature that performs logical NOT operations on magnetic logic signals. When this two-terminal ferromagnetic structure is incorporated into a magnetic feedback loop, the junction performs a frequency division operation on an applied oscillating magnetic field. Up to 11 of these junctions are then directly linked together to create a magnetic shift register.

540 citations

Journal ArticleDOI
TL;DR: Various algorithms which have been suggested for generating full length nonlinear shift register sequences of length $2^n $ are discussed.
Abstract: Shift registers have been used to generate sequences of 0’s and 1’s for over thirty years. A wide variety of applications has been made of these sequences. Principally, communications have made use of the sequences generated.One particular class of shift register sequences for which applications exist is the full length nonlinear shift register sequences. These sequences are periodic and of length $2^n $ and all $2^n $ different binary n-tuples appear exactly one time in a periodic portion of the sequence. In this paper we discuss various algorithms which have been suggested for generating these sequences.

448 citations


Network Information
Related Topics (5)
Electronic circuit
114.2K papers, 971.5K citations
82% related
Integrated circuit
82.7K papers, 1M citations
81% related
CMOS
81.3K papers, 1.1M citations
79% related
Decoding methods
65.7K papers, 900K citations
76% related
Amplifier
163.9K papers, 1.3M citations
76% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202326
202288
2021107
2020361
2019438
2018430