scispace - formally typeset
Search or ask a question

Showing papers on "Silicon nitride published in 1981"


Patent
Jacob Riseman1, Paul J. Tsang1
30 Dec 1981
TL;DR: In this paper, a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another, and an insulating layer which may be designated to be in part the gate dielectric layer is formed over the isolation pattern surface.
Abstract: Methods for fabricating a semiconductor integrated circuit having a sub-micrometer gate length field effect transistor devices are described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. An insulating layer which may be designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a first polycrystalline silicon layer is formed thereover. A masking layer such as silicon dioxide, silicon nitride or the like is then formed upon the first polycrystalline layer. The structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness conductive layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices. Ion implantation is then accomplished to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide or polycide (a combination of layers of polycrystalline silicon and metal silicide).

171 citations


Journal ArticleDOI
TL;DR: In this article, the authors studied the mechanism of plasmaenhanced vapor deposition of silicon nitride by varying process parameters, such as substrate temperature, rf power, reactant gas ratio, and total pressure.
Abstract: The mechanism of plasma‐enhanced vapor deposition of silicon nitride is studied by varying process parameters, such as substrate temperature, rf power, reactant gas ratio, and total pressure. The film composition (Si, N, O, and H) is determined by electron microprobe and infrared analysis. From these analyses, it is established that the film composition is determined not only by the reactant gas ratio, but also by a combined function of the rf power and total pressure in terms of , with a system‐dependent factor. The dependence of film composition on can be related to the radical generation processes. The substrate temperature is found to affect the film composition as well. Greater substrate temperature produces films with less hydrogen and more nitrogen, and hence, higher density. The film dielectric property and plasma etching rate are both studied and found to be dependent on the film composition. Finally, a three‐step deposition mechanism, namely, radical generation, radical adsorption, and adatom rearrangement, is proposed to explain the reaction scheme, and an ion incorporation mechanism is proposed to explain the change of film physical properties.

127 citations


Journal ArticleDOI
TL;DR: In this article, a thin-film field effect transistor was fabricated using glowdischarge amorphous silicon as the semiconductor and silicon nitride as the insulator, and the transistor operated in the electron (n type) accumulation mode and by changing the gate potential from zero to only 3 V a change in the source-drain conductance was obtained.
Abstract: A thin‐film field‐effect transistor has been fabricated using glow‐discharge amorphous silicon as the semiconductor and silicon nitride as the insulator. The transistor operates in the electron (n type) accumulation mode and by changing the gate potential from zero to only 3 V a change in the source‐drain conductance of greater than four orders of magnitude is obtained. The results imply upper limits to the density of gap states in amorphous silicon and interface states at the amorphous silicon‐silicon nitride interface of 3×1016 cm−3 eV−1 and 5×1011 cm−2 eV−1, respectively.

122 citations


Journal ArticleDOI
J.Ashley Taylor1
TL;DR: In this article, the chemical bonding of Si in silicon nitride thin films has been studied using XPS and the kinetic energies of Si KLL and Si LVV lines and the binding energies of the photoelectron lines along with their Auger parameters have been tabulated for sputter deposited, plasma deposited and CVD Si nitride films.

106 citations


Journal ArticleDOI
TL;DR: In this paper, a composite encapsulation layer of silicon dioxide and silicon nitride was used in conjunction with zone melting by a moveable strip heater for the recrystallization of thin silicon films on silicon dioxide.
Abstract: We report a process for the recrystallization of thin silicon films on silicon dioxide that uses a composite encapsulation layer of silicon dioxide and silicon nitride in conjunction with zone melting by a moveable strip heater. The recrystallization process achieves large-grained

97 citations


Patent
27 Nov 1981
TL;DR: In this article, an ion implantation method was used to obtain the semiconductor device having a high reliability by a method wherein, before performing the anode formation of the silicon nitride film on a polycrystalline silicon layer, the speed of formation of a nitric oxide film stuck on the surface and the side of the poly crystal silicon layer is changed relatively by performing ion implantations.
Abstract: PURPOSE:To obtain the semiconductor device having a high reliability by a method wherein, before performing the anode formation of the silicon nitride film on a polycrystalline silicon layer, the speed of formation of the nitride film stuck on the surface and the side of the polycrystalline silicon layer is changed relatively by performing an ion implantation. CONSTITUTION:On a silicon single crystal substrate 31, a P type base region 32 and a silicon dioxide layer 33 are formed and the emitter window having the desired shape is provided. Then, after the polycrystalline silicon layer 34, wherein impurities were added, has been provided by implanting boron, an emitter region 35 is formed by performing a heat diffusing method using said polycrystalline layer 34 as the source of diffusion. Then, the window to be used for the contact of a metal electrode and the base region 32 is formed on a layer 33, a base electrode contacting region 36 of a high density is formed and the silicon nitride film for surface stabilization is grown in vapor-phase on the whole surface of the substrate. Then, a silicon nitride film 38 is formed on the layer 34 by performing a phosphorous ion implantation, a nitride film 39 is formed on the side, a formation is performed on the film 38 until it is changed into an oxide film and porous oxide films 40 and 41 are formed, thereby enabling to obtain a highly reliable semiconductor device.

69 citations


Patent
16 Nov 1981
TL;DR: In this paper, stable, viscous polymers of silicon, nitrogen and hydrogen are formed by reacting a halosilane with ammonia in the presence of a solvent comprising an aliphatic ether, a chloromethane or mixtures thereof.
Abstract: Stable, viscous polymers of silicon, nitrogen and hydrogen are formed by reacting a halosilane with ammonia in the presence of a solvent comprising an aliphatic ether, a chloromethane or mixtures thereof. After the solvent has been removed from the reaction product, the polymer can be poured into a container of desired shape and then can be sintered to form a uniform silicon nitride product.

68 citations


Journal ArticleDOI
TL;DR: In this paper, the nature of bonding in silicon nitride is treated using simple bond-orbital models, and the density of states for β-Si3N4 is calculated for two Si-N-Si bond angles, 120° and 107°.
Abstract: The nature of bonding in silicon nitride is treated using simple bond-orbital models. A nitrogen pπ lone-pair valence band maximum is found. This is due to the planar nitrogen site, which is in turn due to the repulsions between non-bonded second-neighbour silicon atoms. The conduction minimum is found to have a relatively low effective mass and be formed of Si 3s states. The density of states (DOS) for β-Si3N4 is calculated for two Si–N–Si bond angles, 120° and 107°. The DOS at the former angle, which corresponds to a planar nitrogen, shows an upper pπ valence band which has merged into the lower bonding bands at 107°. The effects of non-bonded silicon–silicon repulsions on the planarity of the nitrogen site and likely structure of amorphous silicon nitride are discussed. Unlike vitreous SiO2, commercial silicon nitride contains an appreciable proportion of impurities which may determine electronic transport and low-energy optical properties. The local electronic structure of ≡Si–Si, ≡Si–H, =N–H...

66 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of compositional and microstructural variables and processing conditions on the room temperature thermal diffusivity of hot-pressed and reaction-sintered silicon nitride were determined.
Abstract: The effects of compositional and microstructural variables and processing conditions on the room temperature thermal diffusivity of hot-pressed and reaction-sintered silicon nitride were determined. The thermal diffusivity for hot-pressed silicon nitride increases withβ-content. Maximum thermal diffusivity is reached at about 3 wt % MgO. The higher thermal diffusivity of the β-phase is attributed to its higher purity level and the less distorted crystal structure compared to theα-phase. In reaction-sintered nitride the thermal diffusivity is strongly influenced by the relative amount and needle-like morphology of theα-phase. Correlations of the thermal diffusivity with mechanical properties are discussed.

66 citations


Journal ArticleDOI
TL;DR: The elemental composition of the non-crystalline intergranular phase in two MgO-fluxed hot-pressed silicon nitrides, determined by X-ray microanalysis and electron energy loss spectroscopy in the transmission electron microscope, is reported in this article.
Abstract: The elemental composition of the noncrystalline intergranular phase in two MgO-fluxed hot-pressed silicon nitrides, determined by X-ray microanalysis and electron energy loss spectroscopy in the transmission electron microscope, is reported. The composition is similar in both and lies near the SiO2-MgSiO3 tie line with impurities of Ca, Al, and Cl. No nitrogen could be detected in the noncrystalline phase, implying that the nitrogen concentration was below the experimental detectability limit.

66 citations


Journal ArticleDOI
TL;DR: In this article, CVD Si-nitride films as transparent dielectric satisfy all requirements for achieving MIS/IL solar cells with high efficiency and long term stability, and the highest known QN/q values (> 1013cm−2) combined with low values of Nit have been achieved.
Abstract: It is demonstrated that CVD Si-nitride films as transparent dielectric satisfy all requirements for achieving MIS/IL solar cells with high efficiency and long term stability. Deposited on silicon by the SiH4/NH3 reaction at temperatures lower than usual (between 600° and 650°C) fixed positive interface charge densities QN/q up to 7 × 1012 cm−2 with excellent stability have been obtained. Utilizing the Si-nitride charge storage effect, the highest known QN/q values (> 1013cm−2) combined with low values of Nit have been achieved. The charge distribution is discussed and an energy band diagram modified according to new analytical results is presented. MIS/IL solar cells with AM1 efficiencies of 15% (active area) and high UV sensitivity have been obtained.

Journal ArticleDOI
TL;DR: In this paper, a new procedure for plasmaenhanced thermal nitridation of silicon is reported, where highly purified ammonia plasma is generated in a quartz tube by radiofrequency power heating induction-coupled and SiC-coated carbon susceptors.
Abstract: A new procedure for plasma‐enhanced thermal nitridation of silicon is reported. Highly purified ammonia plasma is generated in a quartz tube by radio‐frequency power heating induction‐coupled and SiC‐coated carbon susceptors. This system requires no additional electrode in the reaction environment. At a substrate temperature of 1050 °C, thermal silicon nitride films with a thickness above 100 A are grown for 150 min in background pressures ranging from 10−1 to 10 Torr. The films have a refractive index of 1.90, oxygen contamination of less than 10%, and an etching rate two orders of magnitude smaller than that of a thermal SiO2 film in a solution of NH4F:HF = 7:1.


Patent
Robert P. H. Chang1
13 Mar 1981
TL;DR: Atomic hydrogen, typically produced in a plasma, etches a wide range of materials, including III-V materials and their oxides as discussed by the authors, providing significant possibilities for processing integrated circuits and other devices.
Abstract: Atomic hydrogen, typically produced in a plasma, etches a wide range of materials, including III-V materials and their oxides. GaAs oxide is etched at a faster rate than GaAs, for example, providing significant possibilities for processing integrated circuits and other devices. Silicon is etched preferentially as compared to silicon dioxide or silicon nitride. Native oxides are also conveniently removed by this method prior to other processing steps.

Patent
19 May 1981
TL;DR: A semiconductor device has a passivation layer disposed on a semiconductor body having at least one circuit element therein this paper, which has a density of 2.9-3.05 gr/cm3.
Abstract: A semiconductor device has a passivation layer disposed on a semiconductor body having at least one circuit element therein. This layer is made of a silicon nitride material containing 0.8-5.9 weight-% of H, together with 61-70 weight-% of Si, 25-37 weight-% of N and up to 0.6 weight-% of O and has a density of 2.9-3.05 gr/cm3.

Patent
01 Jun 1981
TL;DR: In this paper, a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide, followed by deposition of a thicker layer of polyimide forming polymer.
Abstract: A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique.

Journal ArticleDOI
TL;DR: In this article, the ESR signal from the defects in plasma-deposited silicon nitride has been observed, for the first time, and it is suggested that most of dangling bonds of nitrogen atoms in the silicon Nitride are passivated by bonded-hydrogen and silicon dangling bonds are mainly responsible for the eSR signal.
Abstract: ESR signal from the defects in plasma-deposited silicon nitride has been observed, for the first time. The g-value (2.0055) is identical with that of silicon dangling bonds in amorphous Si:H, and the linewidth (14.5 G) is two times as large as that of amorphous Si:H for spin densities below 1018 cm-3, above which narrowing of the linewidth takes place as in the case of amorphous Si:H. It is suggested that most of dangling bonds of nitrogen atoms in the silicon nitride are passivated by bonded-hydrogen and silicon dangling bonds are mainly responsible for the ESR signal. A correlation between the spin density and leakage current through the film is also discussed.

Patent
27 Aug 1981
TL;DR: In this article, a dual-layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23).
Abstract: Capacitors or dual layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23). The insulation region formed between the two polycrystalline silicon regions has substantially fewer defects than the insulation regions used in prior art techniques due to the use of a unique process wherein the polycrystalline silicon layer (24) overlying the insulation layer (23) protects the insulation layer from attack during subsequent processing. An improved dielectric strength is provided by forming the insulation region (23) utilizing composite layers of silicon oxide (23a, 23c) and silicon nitride (23b).

Journal ArticleDOI
TL;DR: In this paper, the authors measured the rate of thermal etching on polycrystalline specimens of Si, Sic, and Si3N4 and found that grain-boundary grooves formed by an evaporation process similar to that for decomposition.
Abstract: Polished polycrystalline specimens of Si, Sic, and Si3N4 were heated to high temperatures and the rate of thermal etching was measured. Grain-boundary grooving occurred on silicon by surface diffusion, with a surface-diffusion coefficient given by Silicon carbide surfaces became extremely rough and very little grain-boundary grooving occurred. Silicon nitride decomposed in an N2-H2, atmosphere with an activation energy of 757 kJ/mol, which was very near the activation energy calculated from thermochemical data. The surfaces became fairly rough but grain-boundary grooves formed by an evaporation processsimilar to that for decomposition.

Patent
27 Apr 1981
TL;DR: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions is described in this article.
Abstract: A coplanar CMOS process for fabricating self-aligned gate FETs utilizing high energy, high dose rate ion implants to form the S/D regions In the course of coplanar processing, the gate electrodes and S/D regions are defined Selectively prescribed thicknesses of silicon dioxide are then formed over the top and sidewalls of the gate electrodes, as well as the exposed substrate in the S/D regions Thereafter, a first, silicon nitride layer of controlled thickness is evenly deposited, and is followed by a dry etch step to expose the thin layer of silicon dioxide covering the p-channel FET S/D regions The temperature stability of silicon nitride protects the n-channel FETs from the effects of the high energy levels and currents associated with the ion implant step used to form the S/D regions of the p-channel FETs In contrast, the implant ions readily penetrate the thin oxides over the S/D regions of the p-channel FETs Thereafter, a second, silicon nitride layer of controlled thickness is deposited Again, it is followed by a dry etch step, but now to expose the silicon dioxide covering the n-channel FET S/D regions The succeeding n-channel S/D implant similarly penetrates the silicon dioxide coverings, while the silicon nitride serves as a barrier for the remaining substrate surface After S/D implanting is completed, a highly preferential etchant is used to remove the remaining silicon nitride, while the areas protected by the relatively thin layers of silicon dioxide are substantially unaffected

Patent
08 Oct 1981
TL;DR: In this article, the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements is discussed, and the structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip.
Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Patent
31 Aug 1981
TL;DR: In this paper, a film body consisting mainly of α-type crystal and containing particle-like TiN deposited in the crystal and having a crystal orientation of crystal face (OOl) was constructed by means of a blowpipe composed of a pipe assembly.
Abstract: Titanium-containing silicon nitride film bodies include a film body having an essentially amorphous structure and containing particle-like titanium nitride, a film body consisting mainly of α-type crystal and containing particle-like TiN deposited in the crystal and having a crystal orientation of crystal face (OOl), and a film body consisting mainly of β-type crystal and containing column-like TiN deposited in the crystal along the c-axis direction thereof and having a crystal orientation of crystal face (OOl), which are produced by blowing a nitrogen depositing source, a silicon depositing source and a titanium depositing source on a substrate heated at 500°-1,900° C. by means of a blowpipe composed of a pipe assembly to perform chemical vapordeposition reaction.

Patent
13 Mar 1981
TL;DR: An improved liner for crucibles and dies used to melt silicon comprising one or more sheets of graphite each of which has on at least the surface facing the silicon melt a layer of silicon nitride or silicon oxynitride as discussed by the authors.
Abstract: An improved liner for crucibles and dies used to melt silicon comprising one or more sheets of graphite each of which has on at least the surface facing the silicon melt a layer of silicon nitride or silicon oxynitride.

Journal ArticleDOI
TL;DR: In this article, a single-layer X-ray mask with a 30 × 30 mm window and high transparency to visible light was realized using a silicon nitride film as an Xray mask, which has a 15 kg/mm2 and refractive index of 2.3.
Abstract: In the low pressure chemical vapor deposition process, preparation of silicon nitride with low film stress and low refractive index is investigated as a function of deposition temperature and reactant gas ratio SiH2Cl2/NH3. The silicon nitride film with a stress of 15 kg/mm2 and refractive index of 2.3 is formed at the deposition temperature of 850°C and the SiH2Cl2/NH3 ratio of 4/1. Using the film as an X-ray mask, a silicon nitride single-layer X-ray mask is realized, which has a 30 ×30 mm window and has high transparency to visible light.

Journal ArticleDOI
TL;DR: In this article, the same high interface quality as obtained for Si-nitride on monocrystalline silicon could also be achieved for polycrystalline polysilicon, with interface charge densities up to 6.6 × 1012cm-2 and high UV sensitivity of the cells.
Abstract: Plasma enhanced CVD silicon nitride is introduced for the fabrication of inversion layer solar cells on p-type polycrystalline silicon. The same high interface quality as obtained for Si-nitride on monocrystalline silicon could also be achieved for polycrystalline silicon. This includes high interface charge densities up to 6.6 × 1012cm-2and high UV sensitivity of the cells. For 4-cm2polycrystalline metal-insulator-semiconductor inversion layer (MIS/IL) solar cells active area efficiencies up to 13.4 percent (12.3-percent total area efficiency) under AM1 illumination could be reached, the highest values yet reported for polycrystalline silicon inversion layer solar cells on a total area basis. For the coprocessed MIS/IL cells on monocrystalline 0.7-ω. cm p-Si

Journal ArticleDOI
TL;DR: In this paper, the redistribution of the compensating dopants, iron or chromium, in semi-insulating indium phosphide has been studied using secondary ion mass spectrometry.
Abstract: The redistribution of the compensating dopants, iron or chromium, in semi‐insulating indium phosphide has been studied using secondary ion mass spectrometry. Annealing with silicon nitride encapsulation results in impurity accumulation within the first 1000A of the surface followed by depletion extending to a depth of ~1 μm. Profiles resulting from the implantation of "neutral" elements (He, B) exhibit accumulation at the surface and also accumulation at the projected range peak. The profiles are explained in terms of gettering of the compensating dopant to defect‐rich regions.

Patent
James Kent Howard1
21 Jul 1981
TL;DR: In this article, a dual or duplex dielectric structure for semiconductor devices was proposed, where one dielectrical layer is comprised of silicon nitride or aluminum oxide and the second dielectrics layer is formed of Ta, Hf, Ti, PbTiO, BaTiO₃, CaTiO ₃ or SrTiOµµ.
Abstract: A capacitor structure for semiconductor devices (1, 2), utilizing a dual or duplex dielectric wherein one dielectric layer (3) is comprised of silicon nitride or aluminum oxide and a second dielectric layer (4) is formed of Ta₂O₅, HfO₂, TiO₂, PbTiO₃, BaTiO₃, CaTiO₃ or SrTiO₃. One electrode (2) is preferably selected from conductive polycrystalline silicon, Ta, and Hf. The other electrode (5) is preferably selected from Al or Au based metals.

Journal ArticleDOI
TL;DR: In this article, the transition region of the bird's beak profile was found to be related to the rigidity of the nitride film and also the oxidation underneath the oxide film via buffer oxide or even a native oxide.
Abstract: Selective oxidation technologies using various thicknesses of silicon nitride formed by low-pressure chemical vapor deposition (LPCVD), plasma assisted nitridation in ammonia, and by nitrogen ion implantation were investigated. The transition region ("bird's beak") profiles were found to be related to the rigidity of the nitride film and also the oxidation underneath the nitride film via the buffer oxide or even a native oxide. With complete elimination of any oxide between Si 3 N 4 and Si achieved by implanting with nitrogen ions or nitriding in an ammonia plasma, a very abrupt transition region was achieved. This new sealed interface localized oxidation (SILO) technology appears to have low crystal defect density suitable for VLSI MOS technology.

Patent
30 Oct 1981
TL;DR: The resistance-heated boat of the present invention is comprised of a heating portion and a crucible portion separated by a heat conducting, substantially non-electrical conducting portion as discussed by the authors.
Abstract: The resistance-heated boat of the present invention is comprised of a heating portion and a crucible portion separated by a heat conducting, substantially non-electrical conducting portion. The heating portion is fabricated of an electrically conductive material capable of being resistance heated to high temperatures. Mixtures of titanium diboride with boron nitride, aluminum nitride or silicon carbide typically provide electrical conductivity in the desired range. Zirconium diboride, mixtures of boron nitride, silicon nitride, aluminum nitride or titanium diboride, or mixtures thereof are also useful. The crucible portion of the boat provides a vaporization surface and is fabricated of materials selected for their ability to provide wettability by the metal to be vaporized, a desired chemical and physical resistance to the metal, or impurities in the metal, to be vaporized and to the vaporization atmosphere. Titanium diboride, zirconium diboride and mixtures thereof are eminently useful in providing a vaporization surface. The separating portion is formed of a heat-conducting, substantially non-electrical-conducting material. The separating portion may also be comprised entirely, or mixtures of, materials containing a major portion, of boron nitride, boron oxide, or mixtures thereof. A preferred material is boron nitride.

Patent
27 Aug 1981
TL;DR: In this article, a silicon carbide of improved quality is obtained by using a liquid silicic acid and carbon in a powdered form, or a precursor of carbon in powder or solution as a carbonaceous substance, and thermally treating these raw materials in a non-oxidative atmosphere.
Abstract: Silicon carbide of improved quality is obtained by using a liquid silicic acid or modified liquid silicic acid as a silicic substance and carbon in a powdered form, a precursor of carbon in a powdered form, or a precursor of carbon in the form of a solution as a carbonaceous substance, and thermally treating these raw materials in a non-oxidative atmosphere. The silicon carbide thus produced is finely divided and in high-purity and suitable for use as raw material for the production of high-strength sintered articles.