Showing papers on "Silicon nitride published in 1999"

Synthesis of cubic silicon nitride

Abstract: Silicon nitride (Si3N4) is used in a variety of important technological applications The high fracture toughness, hardness and wear resistance of Si3N4-based ceramics are exploited in cutting tools and anti-friction bearings1; in electronic applications, Si3N4 is used as an insulating, masking and passivating material2 Two polymorphs of silicon nitride are known, both of hexagonal structure: α- and β-Si3N4 Here we report the synthesis of a third polymorph of silicon nitride, which has a cubic spinel structure This new phase, c-Si3N4, is formed at pressures above 15 GPa and temperatures exceeding 2,000 K, yet persists metastably in air at ambient pressure to at least 700 K First-principles calculations of the properties of this phase suggest that the hardness of c-Si3N4 should be comparable to that of the hardest known oxide (stishovite3, a high-pressure phase of SiO2), and significantly greater than the hardness of the two hexagonal polymorphs

Pendeoepitaxy of gallium nitride thin films

Abstract: Pendeoepitaxy, a form of selective lateral growth of GaN thin films has been developed using GaN/AlN/6H–SiC(0001) substrates and produced by organometallic vapor phase epitaxy. Selective lateral growth is forced to initiate from the (1120) GaN sidewalls of etched GaN seed forms by incorporating a silicon nitride seed mask and employing the SiC substrate as a pseudomask. Coalescence over and between the seed forms was achieved. Transmission electron microscopy revealed that all vertically threading defects stemming from the GaN/AlN and AlN/SiC interfaces are contained within the seed forms and a substantial reduction in the dislocation density of the laterally grown GaN. Atomic force microscopy analysis of the (1120) face of discrete pendeoepitaxial structures revealed a root mean square roughness of 0.98 A. The pendeoepitaxial layer photoluminescence band edge emission peak was observed to be 3.454 eV and is blueshifted by 12 meV as compared to the GaN seed layer.

Memory cell incorporating a chalcogenide element

Abstract: A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disposed over the plugs. Using a poly-spacer process, small pores are formed in the silicon nitride to expose a portion of the polysilicon plugs. A chalcogenide material is disposed in the pores by depositing a layer of chalcogenide material on the silicon nitride layer and planarizing the chalcogenide layer to the silicon nitride layer using CMP. A layer of TiN is next deposited over the plugs, followed by a metallization layer. The TiN and metallization layers are then masked and etched to define memory cell areas.

Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window

Abstract: An oxide etching process, particularly useful for selectively etching oxide (18) over a feature (24) having a non-oxide composition, such as silicon nitride and especially when that feature has a corner (26) that is prone to faceting during the oxide etch. One aspect of the invention uses one of four hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), octafluoropentadiene (C5F8), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10 °C and is commercially available. Another aspect of the invention uses an unsaturated fluorocarbon such as pentafluoropropylene (C3HF5), and trifluoropropyne (C3HF3), both of which have boiling points below 10 °C and are commercially available. The fluorocarbon together with a substantial amount of a noble gas such as argon or xenon is excited into a high-density plasma in a reactor which is inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, one of two two-step etch process is used. In the first, the source and bias power are reduced towards the end of the etch. In the second, the fluorocarbon is used in the main step to provide a good vertical profile and a more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner. The same chemistry can be used in a magnetically enhanced reactive ion etcher (MERIE), preferably with an even larger amount of argon.

Metal-organic atomic-layer deposition of titanium-silicon-nitride films

Abstract: Titanium–silicon–nitride films were grown by metal–organic atomic-layer deposition at 180 °C. When silane was supplied separately in the sequence of a tetrakis(dimethylamido) titanium pulse, silane pulse, and ammonia pulse, the Si content in the deposited films and the deposition thickness per cycle remained almost constant at 18 at. % and 0.22 nm/cycle, even though the silane partial pressure varied from 0.27 to 13.3 Pa. Especially, the Si content dependence is strikingly different from the conventional chemical-vapor deposition. The capacitance–voltage measurement revealed that the Ti–Si–N film prevents the diffusion of Cu up to 800 °C for 60 min. Step coverage was approximately 100% even on the 0.3 μm diam hole with slightly negative slope and 10:1 aspect ratio.

Method for etching a trench having rounded top and bottom corners in a silicon substrate

Abstract: The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

Optimised antireflection coatings for planar silicon solar cells using remote PECVD silicon nitride and porous silicon dioxide

Abstract: Silicon nitride (SiN) films fabricated by remote plasma-enhanced chemical vapour deposition (RPECVD) have recently been shown to provide an excellent electronic passivation of silicon surfaces. This property, in combination with its large refractive index, makes RPECVD SiN an ideal candidate for a surface-passivating antireflection coating on silicon solar cells. A major problem of these films, however, is the fact that the extinction coefficient increases with increasing refractive index. Hence, a careful optimisation of RPECVD SiN based antireflection coatings on silicon solar cells must consider the light absorption within the films. Optimal optical performance of silicon solar cells in air is obtained if the RPECVD SiN films are combined with a medium with a refractive index below 1·46, such as porous SiO2. In this study, the dispersion of the refractive indices and the extinction coefficients of RPECVD SiN, porous SiO2, and several other relevant materials (MgF2, TiOx, ZnS, B270 crown glass, soda lime glass, ethylene vinyl acetate and resin as used in commercial photovoltaic modules) are experimentally determined. Based on these data, the short-circuit currents of planar silicon solar cells covered by RPECVD SiN and/or porous SiO2 single- and multi-layer antireflection coatings are numerically maximised for glass-encapsulated as well as non-encapsulated operating conditions. The porous SiO2/RPECVD SiN-based antireflection coatings optimised for these applications are shown to be universally suited for silicon solar cells, regardless of the internal blue or red response of the cells. Copyright © 1999 John Wiley & Sons, Ltd.

Local interconnect structures and methods for making the same

Abstract: The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure. The silicide layer defines a portion of the local interconnect structure, unreacted silicide forming material is removed and an interlevel dielectric is formed over the silicide layer. The interlevel dielectric includes a recess defined substantially over the active area and an electrically conductive material is deposited in the recess. The present invention also provides local interconnect structures.

Enhancement of silicon oxide etch rate and nitride selectivity using hexafluorobutadiene or other heavy perfluorocarbon

Abstract: A plasma etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. A primary fluorine-containing gas, preferably hexafluorobutadiene (C 4 F 6 ), is combined with a significantly larger amount of the diluent gas xenon (Xe) enhance nitride selectivity without the occurrence of etch stop. The chemistry is also useful for etching oxides in which holes and corners have already been formed, for which the use of xenon also reduces faceting of the oxide. For this use, the relative amount of xenon need not be so high. The invention may be used with related heavy fluorocarbons and other fluorine-based etching gases.

Carrier recombination at silicon–silicon nitride interfaces fabricated by plasma-enhanced chemical vapor deposition

Abstract: Using the light-biased microwave-detected photoconductance decay method, injection level dependent measurements of the effective surface recombination velocity Seff at silicon surfaces passivated by plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) films are performed on monocrystalline silicon wafers of different resistivities and doping types. In order to theoretically simulate the measured dependences of Seff on the bulk injection level Δn, the extended Shockley-Read-Hall formalism is used. Simulation input parameters are the energy dependent interface state densities and capture cross sections of the involved interface defects as well as the positive insulator charge density Qf. The energy dependent properties of the interface defects are experimentally determined by means of small-pulse deep-level transient spectroscopy. These measurements reveal the existence of three “deep” silicon dangling bond defects at the Si-SiNx interface with similar interface state densities but very d...

Method for anisotropic plasma-chemical dry etching of silicon nitride layers using a gas mixture containing fluorine

Abstract: An etching gas mixture containing CHF3, SF6 and a non-oxidizing gas such as Ar is used as an etching gas mixture for the anisotropic plasma-chemical dry-etching of a silicon nitride layer differentially or selectively relative to a silicon oxide layer. The gas mixture does not contain oxygen, chlorine, bromine, iodine or halides in addition to the above mentioned constituents, so that the process can be carried out in reactor systems equipped with oxidizable electrodes. By adjusting the gas flow rates or composition ratios of CHF3, SF6, and argon in the etching gas mixture, it is possible to adjust the resulting etching selectivity of silicon nitride relative to silicon oxide, and the particular edge slope angle of the etched edge of the remaining silicon nitride layer. A high etch rate for the silicon nitride is simultaneously achieved.

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Abstract: Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralargescale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

Integrated palladium-based micromembranes for hydrogen separation and hydrogenation/dehydrogenation reactions

Abstract: The present invention relates to gas separation membranes including a metal-based layer (17) having sub-micron scale thicknesses. The metal-based layer (17) can be a palladium alloy supported by ceramic layers such as a silicon oxide layer and a silicon nitride layer. By using MEMS, a series of perforations (holes) (11) can be patterned to allow chemical components to access both sides of the metal-based layer. Heaters and temperature sensing devices can also be patterned on the membrane (16). The present invention also relates to a portable power generation system at a chemical microreactor comprising the gas separation membrane. The invention is also directed to a method for fabricating a gas separation membrane. Due to the ability to make chemical microreactors of very small sizes, a series of reactors can be used in combination on a silicon surface to produce an integrated gas membrane device.

Low dielectric constant materials for copper damascene

Abstract: Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

Hydrogen role on the properties of amorphous silicon nitride

Abstract: We have developed an interatomic potential to investigate structural properties of hydrogenated amorphous silicon nitride. The interatomic potential used the Tersoff functional form to describe the Si–Si, Si–N, Si–H, N–H, and H–H interactions. The fitting parameters for all these interactions were found with a set of ab initio and experimental results of the silicon nitride crystalline phase, and of molecules involving hydrogen. We investigated the structural properties of unhydrogenated and hydrogenated amorphous silicon nitride through Monte Carlo simulations. The results show that depending on the nitrogen content, hydrogen has a different chemical preference to bind to either nitrogen or silicon, which is corroborated by experimental findings. Besides, hydrogen incorporation reduced considerably the concentration of undercoordinated atoms in the material, and consequently the concentration of dangling bonds.

Method to form shallow trench isolations with rounded corners and reduced trench oxide recess

Abstract: A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.

Structural analysis of Ti1−xSixNy nanocomposite films prepared by reactive magnetron sputtering

Abstract: In this paper, we report on the preparation of thin films resulting from additions of Si to TiN matrix, by r.f. reactive magnetron sputtering. Results of X-ray diffraction (XRD) in both θ –2 θ and α –2 θ scans showed that a mixture of two phases is present, where the first is most likely fcc TiN. The higher lattice parameter of this phase, about 0.429 nm (0.424 nm for bulk TiN), could be explained by taking into account that a correction of the residual stress effect on peak positions might slightly decrease the value of the lattice parameter (around 1%). Regarding phase 2, and although the exact nature of its composition is more difficult to evaluate, we believe that it is also a cubic lattice consisting of TiSiN, where the Si could be occupying Ti positions within the TiN lattice. This would explain the low value of the lattice parameter, which by assuming a cubic structure would be 0.418 nm. Concerning texture evolution, phase 1 revealed some variations in preferential growth, which changed from 〈111〉 for low Si additions to 〈220〉 at intermediate Si additions and finally to a weak 〈200〉 texture for large Si additions. A small amorphous region of silicon nitride for large Si additions was also observed. Fourier analysis of XRD patterns showed a decrease in the size of grains for small Si additions when compared to that of TiN. For higher Si contents, only small changes were observed, although a decrease in grain size seems to be the main tendency. The grains are within the range of 4–6 nm. High-resolution transmission electron microscopy (HRTEM) on Ti 0.63 Si 0.37 N 1.12 confirmed this nanocrystalline nature of the grains, revealing grains with sizes of about 2–3 nm.

Manufacture of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To prevent displacement in overlap of a pattern due to the expansion and contraction of a substrate. SOLUTION: An excess film 3 in the peripheral section of a chip is removed beforehand, and a substrate 1 is returned (S3) to its size close to an original size 1a in a shrunk substrate 1b (S2) by depositing a film (a silicon nitride film 3) having large stresses on the substrate (S1), and element isolation patterns 52 are formed onto the residual silicon nitride films 3-1. That is, the displacement in overlap resulting from the expansion and contraction of the substrate can be prevented, because the manufacture of the semiconductor device is constituted of a first process, in which the silicon nitride film 3 is removed except an element region in the silicon nitride film formed onto the substrate 1, a second process in which a mask for forming an element-region pattern is formed of the silicon nitride film 3 which remains after the first process, and a third process in which the substrate 1 is oxidized after the second process, then an element-isolation oxide film is shaped and the mask as the mask of oxidation is removed.

Method for fabricating a concave bottom oxide in a trench

Abstract: A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Excess silicon at the silicon nitride/thermal oxide interface in oxide–nitride–oxide structures

Abstract: The chemical composition and structure of Si3N4/thermal (native and wet) SiO2 interface in oxide–nitride–oxide structures are studied by using secondary ion mass spectroscopy, electron energy loss spectroscopy (EELS) and Auger electron spectroscopy (AES) measurements. EELS and AES experiments show the existence of excess silicon at the Si3N4/thermal SiO2 interface. Excess silicon (Si–Si bonds) at Si3N4/SiO2 interface exists in the form of Si-rich silicon oxynitride. Numerical simulation of the Si–Si bond’s electronic structure by using semiempirical quantum-chemical method (MINDO/3) shows that Si–Si defects act as either electron or hole traps. This result explains the abnormally large electron and hole capturing at this interface reported earlier.

A composition and method for selectively etching a silicon nitride film

Abstract: The invention relates to an aqueous phosphoric acid etch bath composition with a readily soluble silicon containing composition. The baths are used in the etching step of composite semiconductor device manufacturing.

Mechanisms of deformation of silicon nitride and silicon carbide at high temperatures

Abstract: This paper compares the relative merits of liquid-phase sintered β -Si 3 N 4 with sintered α -SiC for high-temperature applications. These materials represent two extremes of ceramic microstructure: liquid-phase sintered β -Si 3 N 4 contains grains that are coated by a second phase, whereas sintered α -SiC contains grains that are in direct crystalline contact. As will be shown, the mechanical behavior of the two materials differs substantially. At temperatures up to 1500 °C, sintered α -SiC is a creep-resistant solid. At room temperature, however, it is brittle, K Ic =(2–4) MPa·m 1/2 , and has a low bending strength, σ b =(400–500) MPa. By contrast, liquid-phase sintered β -Si 3 N 4 is not as creep resistant since it contains a residual sintering aid at its grain boundaries that deforms at a lower temperature than the silicon nitride grains. Hence, its temperature capability is less than that of sintered α -SiC. Silicon nitride is, however, tougher, K Ic =(6–8) MPa·m 1/2 , and stronger, σ b =(700–1000) MPa, than sintered α -SiC. Deformation of liquid-phase sintered β -Si 3 N 4 , and other ceramics with a second phase at the grain boundaries, depends on the refractoriness of that phase, the more refractory the phase, the more resistant the material is to creep. Experimental results on β -Si 3 N 4 suggest that toughness decreases as creep resistance increases; hence, a trade-off must be made between creep resistance and material toughness to achieve an optimal high temperature microstructure.

In situ deposition and integration of silicon nitride in a high density plasma reactor

Abstract: A method of depositing a dielectric film on a substrate, comprising depositing a silicon oxide layer on the substrate; and treating the dielectric layer with oxygen. A layer of FSG having a fluorine content of greater than 7%, as measured by peak height ratio, deposited by HDP CVD, is treated with an oxygen plasma. The oxygen treatment stabilizes the film. In an alternative embodiment of the invention a thin (<1000 Å thick) layer of material such as silicon nitride is deposited on a layer of FSG using a low-pressure strike. The low pressure strike can be achieved by establishing flows of the process gases such that the pressure in the chamber is between 5 and 100 millitorr, turning on a bias voltage for a period of time sufficient to establish a weak plasma, which may be capacitively coupled. After the weak plasma is established a source voltage is turned on and subsequently the bias voltage is turned off. Silicon nitride layers deposited using the low pressure strike exhibit good uniformity, strong adhesion, and inhibit outgassing from underlying layers.

Dispersant‐Binder Interactions in Aqueous Silicon Nitride Suspensions

Abstract: The interaction of dispersant and binder on the surface of particles was studied to identify the effect of these additives on aqueous ceramic powder processing. Poly(methacrylic acid) (PMAA) and poly(vinyl alcohol) (PVA) were used as the dispersant and binder, respectively. The adsorption isotherms of the organic additives on silicon nitride were determined. The adsorption of PMAA was differentiated from PVA in the mixed additive system via ultraviolet spectroscopy. The electrokinetic behavior of silicon nitride was measured by using an electrokinetic sonic amplitude analyzer. As the PMAA concentration increased, the isoelectric point (pHiep) of silicon nitride shifted from pH 6.7 ± 0.1 to acidic pH values. The magnitude of the shift depended on the surface coverage of PMAA. PVA did not affect the pHiep of suspensions but did cause a moderate decrease in the near-surface potential. Finally, the rheological behavior of silicon nitride suspensions was measured to assess the stability of particles against flocculation in aqueous media; this behavior was subsequently correlated with the electrokinetic and adsorption isotherm data.