Showing papers on "Silicon nitride published in 2001"

Graded thin films

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Formation of Long-Range-Ordered Nanocrystal Superlattices on Silicon Nitride Substrates

Abstract: Particle−particle and particle−substrate interactions cause nanocrystals to self-assemble into superlattice structures upon drying from a colloidal suspension on a solid surface. Rapid dewetting of a volatile solvent, however, can significantly undermine the degree of ordering. We demonstrate here that by increasing the concentration of the nonvolatile dodecanethiol ligand, dewetting can be controlled and gold nanocrystal superlattices can be formed on silicon nitride substrates with long range ordering over several microns. Monolayer and bilayer superlattices can be produced by adjusting the nanocrystal concentration. The superlattice structures are robust and are not perturbed by the final dewetting of the solvent.

Band gap engineering of amorphous silicon quantum dots for light-emitting diodes

Abstract: Amorphous silicon quantum dots (a-Si QDs), which show a quantum confinement effect were grown in a silicon nitride film by plasma-enhanced chemical vapor deposition. Red, green, blue, and white photoluminescence were observed from the a-Si QD structures by controlling the dot size. An orange light-emitting diode (LED) was fabricated using a-Si QDs with a mean size of 2.0 nm. The turn-on voltage was less than 5 V. An external quantum efficiency of 2×10−3% was also demonstrated. These results show that a LED using a-Si QDs embedded in the silicon nitride film is superior in terms of electrical and optical properties to other Si-based LEDs.

Silicon-Based Materials from Rice Husks and Their Applications

Abstract: Rice husk (RH) has now become a source for a number of silicon compounds, including silicon carbide, silica, silicon nitride, silicon tetrachloride, zeolite, and pure silicon. The applications of such materials derived from rice husks are very comprehensive. The methods of synthesizing these silicon-based materials from RHs and their applications are reviewed in this paper.

Semiconductor device and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To provide such a structure for a semiconductor device having a microfabricated cell structure that can prevent shortcircuiting resulting from alignment when two contacts with different heights such as a bit contact and a capacity contact become close to each other, without increasing contact resistance of the capacity contact, and to provide a manufacturing method thereof SOLUTION: The semiconductor device includes at least a first contact 4 and a second contact 6 higher than the first contact which share at least one layer made of an interlayer film 3 and are arranged close to each other In this case, the upper surface of the first contact 4 is recessed to the interlayer film 3 wherein the first contact is formed, and a silicon nitride film sidewall 9 is provided from the upper surface of the first contact to the sidewall of the recess within the recess COPYRIGHT: (C)2009,JPO&INPIT

Method of manufacturing a semiconductor device

Abstract: A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a satisfactory shape is obtainable.

Surface passivation of silicon solar cells using plasma-enhanced chemical-vapour-deposited SiN films and thin thermal SiO2/plasma SiN stacks

Abstract: Two different techniques for the electronic surface passivation of silicon solar cells, the plasma-enhanced chemical vapour deposition of silicon nitride (SiN) and the fabrication of thin thermal silicon oxide/plasma SiN stack structures, are investigated. It is demonstrated that, despite their low thermal budget, both techniques are capable of giving an outstanding surface passivation quality on the low-resistivity (∼1 � cm) p-Si base as well as on n + -diffused solar cell emitters with the oxide/nitride stacks showing a much better thermal stability. Both techniques are then applied to fabricate frontand rear-passivated silicon solar cells. Open-circuit voltages in the vicinity of 670 mV are obtained with both passivation techniques on float-zone single-crystalline silicon wafers, demonstrating the outstanding surface passivation quality of the applied passivation schemes on real devices. All-SiN passivated multicrystalline silicon solar cells achieve an open-circuit voltage of 655 mV, which is amongst the highest open-circuit voltages attained on this kind of substrate material. The high open-circuit voltage of the multicrystalline silicon solar cells results not only from the excellent degree of surface passivation but also from the ability of the cell fabrication to maintain a relatively high bulk lifetime (>20 µs) due to the low thermal budget of the surface passivation process.

Monolithic nanofluid sieving structures for DNA manipulation

Abstract: A new technique for fabricating two-dimensional and three-dimensional fluid microchannels for molecular studies includes fabricating a monolithic unit using planar processing techniques adapted from semiconductor electronics fabrication. A fluid gap between a floor layer (12) and a ceiling layer (20) is provided by an intermediate patterned sacrificial layer (14) which is removed by a wet chemical etch. The process may be used to produce a structure such as a filter or artificial gel by using Electron beam lithography to define a square array of 100 nm holes (30) in the sacrificial layer. CVD silicon nitride (54) is applied over the sacrificial layer and enters the array of holes to produce closely spaced pillars. The sacrificial layer can be removed with a wet chemical etch through access holes in the ceiling layer, after which the access holes are sealed with VLTO silicon dioxide (64).

Method of forming graded thin films using alternating pulses of vapor phase reactants

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO 2 ) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a graded transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

Surface recombination velocity of phosphorus-diffused silicon solar cell emitters passivated with plasma enhanced chemical vapor deposited silicon nitride and thermal silicon oxide

Abstract: This work was supported by funding from the Australian Research Council. One of the authors ~J.S.! gratefully acknowledges the support of a Feodor Lynen fellowship by the Alexander von Humboldt Foundation of Germany.

Chemical vapor deposition of barriers from novel precursors

Abstract: The present invention provides a method and precursor for forming a metal and/or metal nitride layer on the substrate by chemical vapor deposition. The organometallic precursor has the formula of (Cp(R)n)xMHy-x, where Cp is a cyclopentadienyl functional group, R is a substituent on the cyclopentadienyl functional group comprising an organic group having at least one carbon-silicon bond, n is an integer from 0 to 5, x is an integer from 1 to 4, M is a metal, and y is the valence of the metal M. A metal, metal nitride, metal carbon nitride, or metal silicon nitride film (118; 119) is deposited on a heated substrate (112) by thermal or plasma enhanced decomposition of the organometallic precursor in the presence of a processing gas, such as hydrogen, nitrogen, ammonia, silane, and combinations thereof, at a pressure of less than about 26.66 hPa (20 Torr). By controlling the reactive gas composition either metal or metal nitride films may be deposited. The deposited metal or metal nitride film (118; 119) may then be exposed to a plasma to remove contaminants, densify the film, and reduce film resistivity.

Multilayer dielectric stack and method

Abstract: A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Anemometer with hot platinum thin film

Abstract: The techniques of micromachining silicon are used for the manufacture of an anemometer with low electric consumption and great sensitivity. To reduce the energy consumption, a suspended membrane of silicon rich silicon nitride SiNx makes it possible to carry out the heat insulation between the heater and the substrate. Platinum (Pt) thin film (3000 A) with titanium (300 A) adhesion layer on SiNx/Si substrate is used for the hot resistor. Among the methods of Pt deposition tested, electron beam evaporation gives the best results for the temperature coefficient of resistance (TCR) of Pt. Its response time is about 6 ms. Sensitivity in laminar and turbulent flow range are respectively 4.80 mV/(m/s)0.45/mW and of 0.705 mV/(m/s)0.8/mW for about 20 mW power supplied. The experiments show that the temperature rise of the sensor is not sensitive to the ambient temperature. Moreover, sensor response shows no significant changes according to parallel or perpendicular orientation of the gas flow.

Large area dense nanoscale patterning of arbitrary surfaces

Abstract: We demonstrate a large-area fabrication of hexagonally ordered metal dot arrays with an area density of ∼1011/cm2. We produced 20 nm dots with a 40 nm period by combining block copolymer nanolithography and a trilayer resist technique. A self-assembled spherical-phase block copolymer top layer spontaneously generated the pattern, acting as a template. The pattern was first transferred to a silicon nitride middle layer by reactive ion etch, producing holes. The nitride layer was then used as a mask to further etch into a polyimide bottom layer. The metal dots were produced by an electron beam evaporation followed by a lift-off process. Our method provides a viable route for highly dense nanoscale patterning of different materials on arbitrary surfaces.

Method for forming nitride spacer by using atomic layer deposition

Abstract: The present invention provides a method for forming a silicon nitride spacer by using an atomic layer deposition (ALD) method. The procedure of the ALD is to use a first kind of excess gas as a reactant air and thus produce a first mono-layer solid phase of the first reactant air on the wafer. When the first chemical reaction is completed, the first excess air is drawn out, and then the second excess air is released to deposit a second mono-layer solid phase of the second reactant air on the first mono-layer solid phase. In this way, a whole deposited layer with a layer of the first mono-layer solid phase, a layer of the second mono-layer solid phase, and so on are stepwise formed on the wafer surface. The ALD method is a time consuming task in deposition process such as in the generation of 0.35 μm to 0.5 μm of VLSI ages. However, in the generation of 0.18 μm, 0.13 μm or beyond of VLSI ages, because the device is getting smaller than ever before, the deposition speed of the ALD method is just right on time to meet the demand and is an appropriate method in depositing silicon nitride spacer.

Method of plasma etching of silicon carbide

Abstract: The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH 3 F, an oxygen-containing gas such as O 2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.

Semiconductor device and manufacturing method therefor

Abstract: A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

Semiconductor processing equipment having improved particle performance

Abstract: A ceramic part having a surface exposed to the interior space, the surface having been shaped and plasma conditioned to reduce particles thereon by contacting the shaped surface with a high intensity plasma. The ceramic part can be made by sintering or machining a chemically deposited material. During processing of semiconductor substrates, particle contamination can be minimized by the ceramic part as a result of the plasma conditioning treatment. The ceramic part can be made of various materials such as alumina, silicon dioxide, quartz, carbon, silicon, silicon carbide, silicon nitride, boron nitride, boron carbide, aluminum nitride or titanium carbide. The ceramic part can be various parts of a vacuum processing chamber such as a liner within a sidewall of the processing chamber, a gas distribution plate supplying the process gas to the processing chamber, a baffle plate of a showerhead assembly, a wafer passage insert, a focus ring surrounding the substrate, an edge ring surrounding an electrode, a plasma screen and/or a window.

Composite microelectronic dielectric layer with inhibited crack susceptibility

Abstract: Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.

Experimental Investigation of Thermo-Mechanical Characteristics in Laser-Assisted Machining of Silicon Nitride Ceramics

Abstract: Laser-assisted machining (LAM) of silicon nitride (Si 3 N 4 ) is evaluated for its potential to become an economically viable process in fabricating precision ceramic parts. On-line measurements of cutting force and workpiece temperature are performed, and tool wear and surface integrity are examined. Tool wear characteristics are determined as a function of workpiece temperature, which is measured on-line using a laser pyrometer Tool wear/failure mechanisms are characterized using optical microscopy while application of scanning electron microscopy to heated and machined surfaces, as well as to chips, is used to infer material removal mechanisms and the extent of damage caused by LAM. The sub-surface damage of parts produced by LAM is compared with that of typical ground parts.

CVD syntheses of silicon nitride materials

Abstract: Low hydrogen-content silicon nitride materials are deposited by a variety of CVD techniques, preferably thermal CVD and PECVD, using chemical precursors that contain silicon atoms, nitrogen atoms, or both. A preferred chemical precursor contains one or more N—Si bonds. Another preferred chemical precursor is a mixture of a N-containing chemical precursor with a Si-containing chemical precursor that contains less than 9.5 weight % hydrogen atoms. A preferred embodiment uses a hydrogen source to minimize the halogen content of silicon nitride materials deposited by PECVD.

In situ dielectric stacks

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Very high voltage AlGaN/GaN high electron mobility transistors using a field plate deposited on a stepped insulator

Abstract: We investigate a technique that has the potential to enhance the breakdown voltage ( V br ) of AlGaN/GaN high electron mobility transistors (HEMTs) beyond 1 kV. The technique involves incorporation of a field plate (FP) connected to the gate and placed over a stepped insulator (SI). A comprehensive account of the critical geometrical and material variables controlling the field distribution under the FP is provided. A systematic procedure is given for designing a SIFP device, using 2-D simulation, to obtain the maximum V br with minimum degradation in on-resistance and frequency response. Simulations show that, for a 2-DEG concentration of 1×10 13 cm −2 , the maximum V br achievable with a stepped aluminum nitride (silicon nitride) insulator can be 2.6 (2.3) times higher than that with a uniform insulator; V br ∼1 kV can be obtained using a gate to drain separation as low as ∼7 μm. The methodology of this paper can be extended to the design of SIFP structures in other lateral FETs, such as MESFETs and LD-MOSFETs.

UV pretreatment process for ultra-thin oxynitride formation

Abstract: The oxynitride or oxide layer formed on a semiconductor substrate is pre-treated with UV-excited gas (such as chlorine or nitrogen) to improve the layer surface condition and increase the density of nucleation sites for subsequent silicon nitride deposition The pre-treatment is shown to reduce the root mean square surface roughness of thinner silicon nitride films (with physical thicknesses below 36 Å, or even below 20 Å that are deposited on the oxynitride layer by chemical vapor deposition (CVD)

Absolute photonic band gaps in 12-fold symmetric photonic quasicrystals

Abstract: A recent publication [Nature (London) 404, 740 (2000)] claimed that absolute photonic gaps can be realized in 12-fold quasicrystalline arrangement of small airholes in a matrix of silicon nitride or glass. The result is rather surprising since silicon nitride $(n=2.02)$ and in particular, glass $(n=1.45)$ have rather low refractive index. In this work, we have studied the transmission properties of the same systems by using the multiple-scattering method. We found that the 12-fold triangle-square tiling is indeed very good for the realization of photonic gaps and we found absolute gaps in systems with airholes in dielectric, dielectric cylinders in air, and metal cylinders in air. However, for the case of air-holes in a dielectric background, absolute gaps appear only when the dielectric contrast is sufficiently high, and both silicon nitride and glass have refractive indices below the threshold.

Semiconductor device and method of producing the same

Abstract: A dummy gate electrode is formed before the gate electrode is formed. Extension regions, side wall silicon nitride film, source/drain regions, silicon oxide film, and others are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused to a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method gives a semiconductor device that prevents the deterioration of electrical characteristics caused by short channel effect and parasitic resistance.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Abstract: We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Design and batch fabrication of probes for sub-100 nm scanning thermal microscopy

Abstract: A batch fabrication process has been developed for making cantilever probes for scanning thermal microscopy (SThM) with spatial resolution in the sub-100 nm range. A heat transfer model was developed to optimize the thermal design of the probes. Low thermal conductivity silicon dioxide and silicon nitride were chosen for fabricating the probe tips and cantilevers, respectively, in order to minimize heat loss from the sample to the probe and to improve temperature measurement accuracy and spatial resolution. An etch process was developed for making silicon dioxide tips with tip radius as small as 20 nm. A thin film thermocouple junction was fabricated at the tip end with a junction height that could be controlled in the range of 100-600 nm. These thermal probes have been used extensively for thermal imaging of micro- and nano-electronic devices with a spatial resolution of 50 nm. This paper presents measurement results of the steady state and dynamic temperature responses of the thermal probes and examines the wear characteristics of the probes.