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Silicon nitride

About: Silicon nitride is a research topic. Over the lifetime, 32678 publications have been published within this topic receiving 413599 citations. The topic is also known as: N₄Si₃.


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Journal ArticleDOI
Eugene A. Irene1
TL;DR: In this paper, the authors studied the mechanical stress caused by Si3N4 films on (111) oriented Si wafers and found that the film stress was highly tensile with a magnitude of about 1010 dynes/cm2.
Abstract: The mechanical stress caused by Si3N4 films on (111) oriented Si wafers was studied as a function of the Si3N4 film thickness, deposition rate, deposition temperature and film composition. The Si3N4 films were prepared by the reaction of gaseous SiH4 and NH3 in the temperature range 700–1000°C. The curvature of the Si substrates caused by the Si3N4. films is related to the film stress; the substrate curvature was measured by an optical interference technique. The measured Si3N4. film stress was found to be highly tensile with a magnitude of about 1010 dynes/cm2. For the thickness range of 2000–5000A, there was no change in the measured stress. The total film stress was observed to decrease for decreasing deposition rate and increasing deposition temperature. A large change in film stress was observed for films containing excess Si; the stress decreased with increasing Si content. Based on published values for the thermal expansion coefficients for Si and Si3N4, a published value for Young’s Modulus for Si3N4, and the measured total stress values, a consistent argument is developed in which the total stress consists of a compressive component due to thermal expansion coefficient mismatch and a larger tensile intrinsic stress component. Both the thermal and intrinsic stress components vary with film deposition temperature in directions which decrease the total room temperature stress for higher deposition temperatures.

76 citations

Patent
Shau-Lin Shue1, Jih-Churng Twu1
23 Oct 1998
TL;DR: In this paper, a gate dielectric layer with enhanced hot carrier resistance properties and enhanced dopant diffusion barrier properties within a field effect transistor (FET) has been constructed using thermal annealing.
Abstract: A method for forming a dielectric layer upon a silicon layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon layer. There is then formed through use of a first thermal annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material silicon nitride containing layer upon a partially consumed silicon layer derived from the silicon layer. There is then oxidized through use of a second thermal annealing method employing an oxidizing material containing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer upon a further consumed silicon layer derived from the partially consumed silicon layer. The method is particularly useful in forming a gate dielectric layer with enhanced hot carrier resistance properties and enhanced dopant diffusion barrier properties within a field effect transistor (FET).

76 citations

Journal ArticleDOI
TL;DR: In this paper, the chemistry of glow discharge plasmaenhanced chemical vapor deposition (PECVD) was studied by using vibrating quartz crystal deposition rate monitoring at 200-300°C and line-of-sight mass spectrometry of orifice-sampled reactive neutral species.
Abstract: We have studied the chemistry of glow discharge plasma‐enhanced chemical vapor deposition (PECVD) by using vibrating quartz crystal deposition rate monitoring at 200–300 °C and line‐of‐sight mass spectrometry of orifice‐sampled reactive neutral species. In the deposition of dielectric films from silane plus a large excess of oxidant (NH3, N2, or N2O), the key process factor is the ratio of plasma power to silane supply rate. When enough of the oxidant is activated by the plasma, it completely converts the silane to films which have no excess Si and no Si–H bonding. The critical ratio can be detected by the disappearance of Si2H6 byproduct or by the presence of excess activated oxidant. Nitride deposited from N2 is electrically leaky due to porous microstructure even when deposited using excess activated oxidant. Conversely, nitride deposited from NH3 is nonporous, and when deposited using excess activated oxidant it has a surprisingly low electron trapping rate which is at least as low as that achievable ...

76 citations

Journal ArticleDOI
TL;DR: In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).
Abstract: We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

76 citations

Journal ArticleDOI
TL;DR: In this article, the authors describe the fabrication of amorphous silicon (a-Si:H) thin film transistors (TFTs) on a Kapton substrate which can be permanently deformed into a spherical cap shape.
Abstract: There is a growing interest in the design and fabrication of flexible and rugged electronics particularly for large-area displays and sensor arrays. In this work, we describe the fabrication of amorphous silicon (a-Si:H) thin film transistors (TFTs) on a Kapton substrate which can be permanently deformed into a spherical cap shape. This level of strain would crack uniform a-Si:H device films. To prevent fractures in our TFT structure, the silicon and silicon nitride layers of the TFTs are patterned to create isolated device islands. After deformation, these brittle islands can remain crack-free, and the TFTs achieve comparable device behavior despite average strain in the substrate in excess of 5%.

76 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023245
2022529
2021421
2020686
2019994
2018911