Silicon nitride

About: Silicon nitride is a research topic. Over the lifetime, 32678 publications have been published within this topic receiving 413599 citations. The topic is also known as: N₄Si₃.

The influence of iron on the preparation of silicon nitride from silica

Abstract: The thermodynamics of carbothermal reduction and nitriding of silica in the temperature range 1200 to 1600° C have been evaluated and may be used to determine the conditions required to form silicon nitride, silicon oxynitride or silicon carbide. The products of reaction are, however, frequently dictated by kinetic rather than thermodynamic considerations and the presence of impurities in the silica and carbon reactants is especially important. α-silicon nitride has been prepared from high purity silica and carbon but under identical conditions of temperature and nitrogen pressure the chemistry of the process changes markedly when a small amount of iron is added to the reactants. Below 1320° C iron has no effect and pure α-silicon nitride is formed but with increasing temperature the proportion of silicon carbide in the product increases. Above 1550° C silicon carbide is the stable solid phase in the Si-C-O-N system at 1 atm pressure. The process chemistry has been investigated by high-temperature reaction studies and X-ray diffraction and reaction mechanisms are proposed on the basis of microstructural observations of reactants and products.

A novel bolometer for infrared and millimeter-wave astrophysics

Abstract: We are developing a novel bolometer which uses a fine mesh to absorb radiation. The filling factor of the mesh is small, providing a small heat capacity and a low geometric cross-section to cosmic rays. The mesh is patterned from a free-standing silicon nitride membrane and is thermally isolated by long radial legs of silicon nitride. A thin metallic film evaporated on the mesh absorbs radiation by matching the surface impedance to that of free space. A neutron transmutation doped germanium thermistor attached to the center of the mesh detects the temperature increase from absorbed radiation. The low thermal conductivity and heat capacity of silicon nitride provide improved performance in low background applications. We discuss the theoretical limits of the performance of these devices. We have tested a device at 300 mK with an electrical NEP = 4 × 10-17 W Hz-1/2 and a time constant r = 40 ms.

Silicon nitride powder, silicon nitride sintered body, sintered silicon nitride substrate, and circuit board and thermoelectric module comprising such sintered silicon nitride substrate

Abstract: A silicon nitride sintered body comprising Mg and at least one rare earth element selected from the group consisting of La, Y, Gd and Yb, the total oxide-converted content of the above elements being 0.6-7 weight %, with Mg converted to MgO and rare earth elements converted to rare earth oxides RE x O y . The silicon nitride sintered body is produced by mixing 1-50 parts by weight of a first silicon nitride powder having a β-particle ratio of 30-100%, an oxygen content of 0.5 weight % or less, an average particle size of 0.2-10 μm, and an aspect ratio of 10 or less, with 99-50 parts by weight of α-silicon nitride powder having an average particle size of 0.2-4 μm; and sintering the resultant mixture at a temperature of 1,800° C. or higher and pressure of 5 atm or more in a nitrogen atmosphere.

Method for forming a vertical transistor with a stacked capacitor DRAM cell

Abstract: There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.