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Silicon nitride

About: Silicon nitride is a research topic. Over the lifetime, 32678 publications have been published within this topic receiving 413599 citations. The topic is also known as: N₄Si₃.


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Patent
24 Apr 1986
TL;DR: In this paper, the authors describe the formation of sealed cavity structures suitable for use as pressure transducers on a single surface of a semiconductor substrate by depositing polycrystalline silicon layer from silane gas over a relatively large silicon dioxide post and smaller silicon dioxide ridges leading outwardly from the post.
Abstract: Sealed cavity structures suitable for use as pressure transducers are formed on a single surface of a semiconductor substrate (20) by, for example, deposit of a polycrystalline silicon layer (32) from silane gas over a relatively large silicon dioxide post (22) and smaller silicon dioxide ridges (27) leading outwardly from the post. The polysilicon layer is masked and etched to expose the outer edges of the ridges and the entire structure is then immersed in an etchant which etches the silicon dioxide forming the ridges and the post but not the substrate (20) or the deposited polysilicon layer (32). A cavity structure results in which channels (35) are left in place of the ridges and extend from communication with the atmosphere to the cavity (36) left in place of the post. The cavity (36) may be sealed off from the external atmosphere by a second vapor deposition of polysilicon or silicon nitride, which fills up and seals off the channels (35), or by exposing the substrate and the structure thereon to an oxidizing ambient which results in growth of silicon dioxide in the channels sufficient to seal off the channels. Deflection of the membrane spanning the cavity occurring as a result of pressure changes, may be detected, for example, by piezoresistive devices formed on the membrane.

162 citations

Patent
01 Sep 1999
TL;DR: In this article, the authors present methods of forming local interconnect structures for integrated circuits, which includes depositing a silicon source layer over a substrate having at least one topographical structure thereon.
Abstract: The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure. The silicide layer defines a portion of the local interconnect structure, unreacted silicide forming material is removed and an interlevel dielectric is formed over the silicide layer. The interlevel dielectric includes a recess defined substantially over the active area and an electrically conductive material is deposited in the recess. The present invention also provides local interconnect structures.

162 citations

Journal ArticleDOI
TL;DR: In this article, the processes used to achieve highly uniform nanoporous dielectric films, high-aspect-ratio nanotextured silicon, silicon nitride dot arrays, silicon pillar arrays, and silicon tip arrays are described.
Abstract: Self-assembled diblock copolymer thin films are used as sacrificial layers for the transfer of dense nanoscale patterns into more robust materials. We detail the processes used to achieve highly uniform nanoporous dielectric films, high-aspect-ratio nanotextured silicon, silicon nitride dot arrays, silicon pillar arrays, and silicon tip arrays. All techniques are compatible with standard semiconductor fabrication processes. We also discuss the possible applications of each resulting nanometer-scale structure, including high surface area substrates for capacitors and biochips, quantum dot arrays for nonvolatile memories, and silicon pillar arrays for vertical transistors or field-emission displays.

162 citations

Patent
17 Oct 2005
TL;DR: In this article, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structures are to be formed.
Abstract: Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structure is to be formed. The spacer structure may be formed over the base structure by depositing a first layer comprising silicon nitride on the base structure, depositing a second layer comprising a silicon-based dielectric material on the first layer, and depositing a third layer comprising silicon nitride on the second layer. The first, second, and third layers are deposited in a single processing reactor.

162 citations

Journal ArticleDOI
TL;DR: In this paper, laser-assisted machining of silicon nitride (Si 3 N 4 ) is evaluated for its potential to become an economically viable process in fabricating precision ceramic parts.
Abstract: Laser-assisted machining (LAM) of silicon nitride (Si 3 N 4 ) is evaluated for its potential to become an economically viable process in fabricating precision ceramic parts. On-line measurements of cutting force and workpiece temperature are performed, and tool wear and surface integrity are examined. Tool wear characteristics are determined as a function of workpiece temperature, which is measured on-line using a laser pyrometer Tool wear/failure mechanisms are characterized using optical microscopy while application of scanning electron microscopy to heated and machined surfaces, as well as to chips, is used to infer material removal mechanisms and the extent of damage caused by LAM. The sub-surface damage of parts produced by LAM is compared with that of typical ground parts.

162 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023245
2022529
2021421
2020686
2019994
2018911