Silicon nitride

About: Silicon nitride is a research topic. Over the lifetime, 32678 publications have been published within this topic receiving 413599 citations. The topic is also known as: N₄Si₃.

Structural properties of amorphous silicon nitride

Abstract: We developed an empirical potential for interactions between Si and N to describe silicon nitride systems using the Tersoff functional form. The fitting parameters were found using a set of ab initio and experimental results of the crystalline phase. Using this empirical model, we explored the structural properties of amorphous silicon nitride through Monte Carlo simulations, and compared them to available experimental data. The good description of the $a\ensuremath{-}{\mathrm{SiN}}_{x}$ system for a wide range of nitrogen contents $(0lxl1.5)$ shows the reliability of this model.

Transistor with low resistance tip and method of fabrication in a CMOS process

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Low temperature fabrication of immersion capacitive micromachined ultrasonic transducers on silicon and dielectric substrates

Abstract: A maximum processing temperature of 250/spl deg/C is used to fabricate capacitive micromachined ultrasonic transducers (CMUTs) on silicon and quartz substrates for immersion applications. Fabrication on silicon provides a means for electronics integration via post-complementary metal oxide semiconductor (CMOS) processing without sacrificing device performance. Fabrication on quartz reduces parasitic capacitance and allows the use of optical displacement detection methods for CMUTs. The simple, low-temperature process uses metals both as the sacrificial layer for improved dimensional control, and as the bottom electrode for good electrical conductivity and optical reflectivity. This, combined with local sealing of the vacuum cavity by plasma-enhanced chemical-vapor deposition of silicon nitride, provides excellent control of lateral and vertical dimensions of the CMUTs for optimal device performance. In this paper, the fabrication process is described in detail, including process recipes and material characterization results. The CMUTs fabricated for intravascular ultrasound (IVUS) imaging in the 10-20 MHz range and interdigital CMUTs for microfluidic applications in the 5-20 MHz range are presented as device examples. Intra-array and wafer-to-wafer process uniformity is evaluated via electrical impedance measurements on 64-element ring annular IVUS imaging arrays fabricated on silicon and quartz wafers. The resonance frequency in air and collapse voltage variations are measured to be within 1% and 5%, respectively, for both cases. Acoustic pressure and pulse echo measurements also have been performed on 128 /spl mu/m/spl times/32 /spl mu/m IVUS array elements in water, which reveal a performance suitable for forward-looking IVUS imaging at about 16 MHz.