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Silicon nitride

About: Silicon nitride is a research topic. Over the lifetime, 32678 publications have been published within this topic receiving 413599 citations. The topic is also known as: N₄Si₃.


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Journal ArticleDOI
TL;DR: In this paper, a series of turning tests were conducted on a number of different cutting-tool materials to machine an Al/25 vol% SiC metal-matrix composite and the influence of the cutting speed on the tool wear, the surface finish, and the cutting forces was established for each tool material.

125 citations

Journal ArticleDOI
TL;DR: In this paper, a high-temperature pressure sensor based on polycrystalline 3C-SiC piezoresistors and fabricated by bulk micromachining the underlying 100mm diameter (100) silicon substrate was presented.
Abstract: This paper explores the development of high-temperature pressure sensors based on polycrystalline and single-crystalline 3C-SiC piezoresistors and fabricated by bulk micromachining the underlying 100-mm diameter (100) silicon substrate. In one embodiment, phosphorus-doped APCVD polycrystalline 3C-SiC (poly-SiC) was used for the piezoresistors and sensor diaphragm, with LPCVD silicon nitride employed to electrically isolate the piezoresistor from the diaphragm. These piezoresistors fabricated from poly-SiC films deposited at different temperatures and doping levels were characterized, showing -2.1 as the best gauge factor and exhibited a sensitivities up to 20.9-mV/V*psi at room temperature. In a second embodiment, epitaxially-grown unintentionally nitrogen-doped single-crystalline 3C-SiC piezoresistors were fabricated on silicon diaphragms, with thermally grown silicon dioxide employed for the piezoresistor electrical isolation from the diaphragm. The associated 3C-SiC/SiO/sub 2//Si substrate was fabricated by bonding a (100) silicon wafer carrying the 3C-SiC onto a silicon wafer with thermal oxide covering its surface. The 3C-SiC handle wafer was then etched away in KOH. The diaphragm was fabricated by time etching the silicon substrate. The sensors were tested at temperatures up to 400/spl deg/C and exhibited a sensitivity of 177.6-mV/V*psi at room temperature and 63.1-mV/V*psi at 400/spl deg/C. The estimated longitudinal gauge factor of 3C-SiC piezoresistors along the [100] direction was estimated at about -18 at room temperature and -7 at 400/spl deg/C.

124 citations

Patent
12 Jan 2007
TL;DR: In this article, the authors proposed a method for processing semiconductor devices that includes providing a semiconductor substrate, which includes forming a pad oxide layer over the substrate and forming a silicon nitride layer over it.
Abstract: A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.

124 citations

Journal ArticleDOI
01 Jun 1993-Wear
TL;DR: In this article, the effect of load and temperature on wear was investigated on a hot isostatically-pressed silicon nitride under various test conditions in self-mated sliding tests in air.

124 citations

Journal ArticleDOI
TL;DR: In this article, an aluminum grid is evaporated onto the a-Si:H-passivated rear of a crystalline silicon solar cell with amorphous silicon rear surface passivation based on a simple process.
Abstract: We have developed a crystalline silicon solar cell with amorphous silicon (a-Si:H) rear-surface passivation based on a simple process. The a-Si:H layer is deposited at 225°C by plasma-enhanced chemical vapor deposition. An aluminum grid is evaporated onto the a-Si:H-passivated rear. The base contacts are formed by COSIMA (contact formation to a-Si:H passivated wafers by means of annealing) when subsequently depositing the front silicon nitride layer at 325°C. The a-Si:H underneath the aluminum fingers dissolves completely within the aluminum and an ohmic contact to the base is formed. This contacting scheme results in a very low contact resistance of 3.5 ±0.2 mΩ cm2 on low-resistivity (0.5 Ω cm) p-type silicon, which is below that obtained for conventional Al/Si contacts. We achieve an independently confirmed energy conversion efficiency of 20.1% under one-sun standard testing conditions for a 4 cm2 large cell. Measurements of the internal quantum efficiency show an improved rear surface passivation compared with reference cells with a silicon nitride rear passivation. Copyright © 2005 John Wiley & Sons, Ltd.

124 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023245
2022529
2021421
2020686
2019994
2018911