Silicon on insulator
About: Silicon on insulator is a(n) research topic. Over the lifetime, 19592 publication(s) have been published within this topic receiving 302534 citation(s). The topic is also known as: SOI.
Richard A. Soref1•Institutions (1)
Abstract: The pace of the development of silicon photonics has quickened since 2004 due to investment by industry and government. Commercial state-of-the-art CMOS silicon-on-insulator (SOI) foundries are now being utilized in a crucial test of 1.55-mum monolithic optoelectronic (OE) integration, a test sponsored by the Defense Advanced Research Projects Agency (DARPA). The preliminary results indicate that the silicon photonics are truly CMOS compatible. RD however, lasing has not yet been attained. The new paradigm for the Si-based photonic and optoelectric integrated circuits is that these chip-scale networks, when suitably designed, will operate at a wavelength anywhere within the broad spectral range of 1.2-100 mum, with cryocooling needed in some cases
31 Mar 1991-
Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 22.214.171.124 Silicon-on-Zirconia (SOZ).- 126.96.36.199 Silicon-on-Spinel.- 188.8.131.52 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 184.108.40.206 "Standard"SIMOX.- 220.127.116.11 Low-dose SIMOX.- 18.104.22.168 ITOX.- 22.214.171.124 SMOXMLD.- 126.96.36.199 Related techniques.- 188.8.131.52 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 184.108.40.206 Hydrogen / rare gas implantation.- 220.127.116.11 Bonding to a stiffener.- 18.104.22.168 Annealing.- 22.214.171.124 Splitting.- 126.96.36.199 Further developments.- 2.9.2 Eltran(R).- 188.8.131.52 Porous silicon formation.- 184.108.40.206 The original Eltran(R) process.- 220.127.116.11 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 18.104.22.168 Most common defects.- 22.214.171.124 Chemical decoration of defects.- 126.96.36.199 Detection of defects by light scattering.- 188.8.131.52 Other defect assessment techniques.- 184.108.40.206 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 220.127.116.11 Accumulation-mode transistor.- 18.104.22.168 Inversion-mode transistor.- 22.214.171.124 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 126.96.36.199 Double-gate SOI MOSFETs.- 188.8.131.52 Triple-gate SOI MOSFETs.- 184.108.40.206 Surrounding-gate SOI MOSFETs.- 220.127.116.11 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 18.104.22.168 Current drive.- 22.214.171.124 Short-channel effects.- 126.96.36.199 Threshold voltage.- 188.8.131.52 Volume inversion.- 184.108.40.206 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 220.127.116.11 Non volatile memory devices.- 18.104.22.168 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.
12 Feb 2004-Nature
TL;DR: An approach based on a metal–oxide–semiconductor (MOS) capacitor structure embedded in a silicon waveguide that can produce high-speed optical phase modulation is described and an all-silicon optical modulator with a modulation bandwidth exceeding 1 GHz is demonstrated.
Abstract: Silicon has long been the optimal material for electronics, but it is only relatively recently that it has been considered as a material option for photonics1. One of the key limitations for using silicon as a photonic material has been the relatively low speed of silicon optical modulators compared to those fabricated from III–V semiconductor compounds2,3,4,5,6 and/or electro-optic materials such as lithium niobate7,8,9. To date, the fastest silicon-waveguide-based optical modulator that has been demonstrated experimentally has a modulation frequency of only ∼20 MHz (refs 10, 11), although it has been predicted theoretically that a ∼1-GHz modulation frequency might be achievable in some device structures12,13. Here we describe an approach based on a metal–oxide–semiconductor (MOS) capacitor structure embedded in a silicon waveguide that can produce high-speed optical phase modulation: we demonstrate an all-silicon optical modulator with a modulation bandwidth exceeding 1 GHz. As this technology is compatible with conventional complementary MOS (CMOS) processing, monolithic integration of the silicon modulator with advanced electronics on a single silicon substrate becomes possible.
01 Jun 2006-IEEE Microwave Magazine
Abstract: The silicon chip has been the mainstay of the electronics industry for the last 40 years and has revolutionized the way the world operates. Today, a silicon chip the size of a fingernail contains nearly 1 billion transistors and has the computing power that only a decade ago would take up an entire room of servers. As the relentless pursuit of Moore's law continues, and Internet-based communication continues to grow, the bandwidth demands needed to feed these devices will continue to increase and push the limits of copper-based signaling technologies. These signaling limitations will necessitate optical-based solutions. However, any optical solution must be based on low-cost technologies if it is to be applied to the mass market. Silicon photonics, mainly based on SOI technology, has recently attracted a great deal of attention. Recent advances and breakthroughs in silicon photonic device performance have shown that silicon can be considered a material onto which one can build optical devices. While significant efforts are needed to improve device performance and commercialize these technologies, progress is moving at a rapid rate. More research in the area of integration, both photonic and electronic, is needed. The future is looking bright. Silicon photonics could provide low-cost opto-electronic solutions for applications ranging from telecommunications down to chip-to-chip interconnects, as well as emerging areas such as optical sensing technology and biomedical applications. The ability to utilize existing CMOS infrastructure and manufacture these silicon photonic devices in the same facilities that today produce electronics could enable low-cost optical devices, and in the future, revolutionize optical communications
06 Jul 1995-Electronics Letters
Abstract: A silicon on insulator material technology based on wafer bonding is described, in which a heat treatment induces an in-depth microslicing of one of the two bonded wafers previously implanted with hydrogen. The basic phenomena, and the first physical and electrical characterisations are discussed briefly.