Showing papers on "Silicon on insulator published in 1976"

Semiconductor device having a body of amorphous silicon

Abstract: An amorphous silicon material, fabricated by the process of a glow discharge in silane, is utilized as the body of semiconductor devices.

Silicon resistive device for integrated circuits

Abstract: A resistive device for use as a current feedback loop in an integrated CMOS shift register circuit is made of an island of polycrystalline silicon with a sheet resistivity of from 10 6 to 10 8 ohms per square. The polycrystalline silicon island has two contacts thereon fashioned in the manner of MOS source and drain contacts and a dummy polycrystalline silicon insulated gate contact thereon. The device structure is designed to be and is fully compatible with CMOS mesa processing. The method for making the device incorporates into the processing steps for CMOS manufacture the formation of polycrystalline silicon islands on the substrate along with monocrystalline silicon islands. In the process, the polycrystalline silicon island is doped, through source and drain mask openings, with impurities of the same conductivity type as that predominating in the polycrystalline silicon island.

Formation of metal nitride oxide semiconductor (MNOS) by ion implantation of oxygen through a silicon nitride layer

Abstract: A layer of silicon nitride (Si 3 N 4 ) is deposited on a silicon substrate. A mask provided with windows representing device structures is then formed over the silicon nitride layer. Oxygen is then implanted through the window portion of the silicon nitride layer into the Si 3 N 4 /Si interface region to form a tunneling insulator interface layer of silicon dioxide (SiO 2 ). The final structure is heat treated and then has the form Si 3 N 4 /SiO 2 /Si. It can be made into a metal nitride oxide semiconductor (MNOS) field effect transistor device by conventional diffusion, ion implant and metallization processes.

Silicon oxide/silicon nitride mask with improved integrity for semiconductor fabrication

Abstract: A semiconductor dielectric layer formed of silicon nitride having a uniform dispersion of carbon therein for providing reduced intrinsic tensile stresses of less than 10 × 10 9 dyn/cm 2 .

P+ Silicon integrated circuit interconnection lines

Abstract: An improved interconnecting line for an integrated circuit comprising a P+ silicon island having an optional first layer of silicon dioxide or a like material thereon and a second layer of silicon nitride or a like material adjacent the first layer, is provided. The line may be manufactured by improvements in the standard P channel MOS or MNOS processing method wherein the line is formed concomitantly with the island upon definition of the silicon. The line may be subsequently coated with silicon dioxide during formation of a gate oxide for a MNOS device and then coated with silicon nitride.

Process for thinning silicon with special application to producing silicon on insulator

Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Silicon Planar Devices Using Nitrogen Ion Implantation

Abstract: Nitrogen implanted polycrystalline silicon layers are used as an oxidation mask in place of conventional silicon nitride layers for the fabrication of planar structured MOS FET's. The stress effect and anomalous oxidation behavior arising from the conventional LOCOS process are thoroughly eliminated. Moreover, the lateral oxidation effect under the oxidation mask was sufficiently reduced. The threshold voltage, unit channel conductance and junction leakage current of devices having nitrogen implanted polycrystalline silicon gates are on the same level as those of conventional LOCOS type devices, which indicates that heavily implanted nitrogen has no effect on the degradation of the substrate crystal. It is also found that silicon dioxide layers behave as diffusion masks against electrically active nitrogen. Another distinct merit of this process is the elimination of the mask alignment margin between the active region and the polycrystalline silicon gate, which makes possible the consequent increase in the device packing density. These results confine the applicability of this process technology to the fabrication of MOS LSI's with a high packing density.

Process for producing an improved dielectrically-isolated silicon crystal utilizing adjacent areas of different insulators

Abstract: Thermoprocessing of integrated-circuit devices and ionizing radiation environments create electronic charges in dielectric isolation materials and in dielectric-semiconductor interface regions. These charges can produce serious alterations in the operating characteristics of the devices and integrated circuits. The deleterious effect of these charges may be greatly reduced by the disclosed process which produces a single-crystal silicon film dielectrically isolated from a polycrystalline silicon support by an underlying insulator of either silicon nitride or silicon dioxide, both of which may be grown by the process at selected locations on the same chip.

Metal oxide-semiconductor capacitors on silicon carbide

Abstract: The purpose of the work discussed in this paper is to determine the feasibility of using Silicon Carbide for making surface field effect devices such as MOSFET's. The device used for making such a determination is the MOS capacitor. This paper discusses briefly the oxidation of Silicon Carbide. The techniques used to make MOS capacitors are outlined, and experimental data are presented which show that it is possible to use Silicon Carbide for constructing surface field effect devices.

Silicon on Sapphire technology

Abstract: access memory, a programmable logic array, a nonvolatile memory etc. The primary difficulties of the SOS structure, such as obtaining the epitaxial silicon films with acceptable electrical characteristics and with reasonably good crystal perfection, seem to be solved from the practical point of view for fabrica¬ tion of MOS transistors on SOS wafer. Basic superiority of the SOS structure compared with the bulk silicon structure has been confirmed through the high density CMOS LSI without any parasitic bipolar transistor effects between n-channel and p-channel transistors, and n-channel MOS LSI with higher speed due to decrease in parasitic capacitance of interconnections of both diffused layers and aluminum and/or polycrystal silicon layers. However, there still remain a number of phenomena which should be revealed prior to development of more advanced version of SOS LSIs. This paper will review the present state of the art, and discuss feasibility of SOS technology, looking at the following matters of interest.

Production of mos structure field effect semiconductor device

Abstract: PURPOSE: To obtain a SOI device of low cost a =nd stable operation by opening holes in the SiC layer on a Si substrate, laminating a Si epitaxial layer thereon and forming channel regions in the portions in contact with the substrate. COPYRIGHT: (C)1978,JPO&Japio

Field effect transistor structure and method for making same

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

Silicon-insulator-polysilicon infrared imaging device and method of making same

Abstract: A layer of epitaxial silicon is grown on a silicon growth substrate, a thinayer of silicon dioxide or other suitable insulator is grown (in the case of silicon dioxide) or deposited (for other insulators) on the epitaxial layer, and a thick layer of polysilicon is grown on the dioxide layer. The silicon growth substrate is then removed, and the epitaxial layer is etched to form islands on the insulator layer. Some of the islands are doped to form an array of infrared sensitive detectors, and a large island is doped to act as CCD region. Electrical leads are fabricated, some to provide drive and output lines for the CCDs, other to provide connections of the detectors to respective CCDs, and yet others to provide common leads for the detectors.

Technology Constraints, Present and Future

Abstract: The technology session of the Asilomar Workshop was oriented mainly towards the constraints of future technologies rather than towards discussing present generally-accepted processes. Four specific areas were highlighted: testing of micro-processors, the future of silicon-on-sapphire (SOS) approaches, the impact of integrated injection logic (I2L), and the role of less-high-density technologies (TTL, ECL, CMOS) in microprocessor development.

Radiation in MOS/SOS Devices.

Abstract: : The electrical properties of thin silicon films deposited on sapphire differ from those of bulk silicon not only because of crystalline imperfections but also because of the proximity of any point within a film to the silicon/sapphire interface. This interface often has a strong influence on SOS device characteristics, especially on the leakage current of irradiated n-channel MOS/SOS transistors. An important aspect of this program has been to define and develop experimental device structures and measurement techniques which would allow a detailed study of silicon/sapphire interfaces. The structures found most suitable for this purpose were junction field-effect transistors (JFET's) and metal-insulator-semiconductor capacitors using the sapphire substrate as gate insulator (back-gate MIS capacitors). Their design and use is described in this report. It is shown that they complement each other in establishing the pre-irradiation and post-irradiation properties of the silicon-on-sapphire films and silicon/sapphire interfaces. The parameters measured included the impurity concentration and mobility as a function of depth into the silicon films, the pre-irradiation silicon/sapphire interface charge, as well as the radiation induced interface charge and changes in the JFET channel conductance as a function of radiation dose.