Showing papers on "Silicon on insulator published in 1977"

Method for manufacturing complementary insulated gate field effect transistors

Abstract: Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

Planar semiconductor devices and method of making the same

Abstract: A semiconductor device includes a region of polycrystalline silicon on a portion of the surface of a body of semiconductor material. A layer of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer.

Method for providing low cost wafers for use as substrates for integrated circuits

Abstract: The method of manufacture of the present invention provides a wafer that is better than a bulk monocrystalline silicon wafer and equivalent to silicon on sapphire (SOS) wafers for use as substrates for integrated circuits. The method comprises taking an inexpensive slab of silicon having crystal orientation and by low pressure CVD, high pressure CVD, or plasma deposition techniques depositing a polycrystalline layer of sapphire on the silicon base. The polycrystalline layer of sapphire is then annealed at an elevated temperature to form a monocrystalline layer having a orientation. A single crystalline layer of silicon having crystal orientation is then epitaxially grown on the sapphire. The resultant multilayer wafer is equivalent in function and reliability to a silicon on sapphire wafer without the commensurate cost.

Technique for threshold control over edges of devices on silicon-on-sapphire

Abstract: A self-aligning technique for doping the edges of metal-oxide-semiconductorevices fabricated on silicon-on-sapphire to eliminate channel-edge conduction at voltages lower than the device threshold voltage without unnecessarily doping the top conducting surface of the device. A thick masking layer is deposited on the silicon layer. The masking layer is etched locally to expose the silicon in the regions between the devices and the exposed silicon is etched to form islands on the sapphire substrate. In a new step, a partial etch of the masking layer is conducted to expose a narrow frame on the top surface and edges of the silicon island. The resulting structure may be doped by any conventional method to ensure heavier doping at the edges than in the transistor channel region.

Method for fabricating semiconductor devices

Abstract: A method for fabricating microminiature, planar semiconductor devices in which the number of defects, in particular, pipes, is minimized. The thicknesses of the thermally grown silicon dioxide and of the silicon nitride masking layers which are used for the formation of limited impurity regions by high temperature diffusion processes within the semiconductor substrate have a specified, limited range. The thickness of the silicon dioxide is between 800A - 3000A and the thickness of the silicon nitride is between around 250A and 600A, preferably 500A. The method is particularly useful in forming extremely small emitter regions in bipolar transistors.

MNOS Memory transistor

Abstract: A memory transistor includes a body of semiconductor material having therein a channel region of one conductivity type and source and drain regions of the opposite conductivity type. A channel insulation is on the surface of the semiconductor body and extends over the channel region. The channel insulation includes a first layer of silicon dioxide directly on the surface of the semiconductor body and a layer of silicon nitride on the silicon dioxide layer. A gate of conductive polycrystalline silicon is preferable provided on the channel insulation. The channel of the transistor is sufficiently narrow so that electrons can be avalanched into the interface between the silicon nitride layer and the silicon dioxide layer completely across the full width of the channel where the electrons can be stored.

Germanium-containing silicon nitride film

Abstract: A germanium-containing silicon nitride film has a germanium content of 0.5 to 10 atomic-% that of the silicon content. Since the film has a much smaller stress than a conventional silicon nitride (Si3 N4) film, it is very suitable as a mask for fabricating a semiconductor device and an insulating or a protective film for a semiconductor device.

Interconnection structure for semiconductor integrated circuits

Abstract: In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

Mos type semiconductor integrated circuit device and process for produ ction of same

Abstract: PURPOSE:Si substrate is used to make a silicon on insulator construction, whereby MOSFET featuring higher speed and higher degree of integration by having the advantages of both conventional MOSFET and SMOS-MOSFET is composed.