Showing papers on "Silicon on insulator published in 1978"

Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides

Abstract: A method for making a semiconductor device is described in which polycrystalline silicon is vacuum deposited and then converted to silicon dioxide thereby providing a number of advantages over direct deposition of silicon dioxide. The method has particular applicability to isoplanar MOSFET integrated circuit manufacturing.

CMOS SOS With narrow ring shaped P silicon gate common to both devices

Abstract: A layer of polycrystalline silicon is coated with a masking layer leaving at least one edge of the silicon layer exposed. A P-type dopant is diffused into the exposed edge of the silicon layer so that the dopant diffuses laterally along the silicon layer a desired distance. The masking layer is then removed and the undoped portion of the silicon layer is removed by an etchant which does not etch the doped portion of the silicon layer. This leaves the narrow strip of the doped silicon which can be used as the gate electrode of an MOS transistor and/or as an interconnection in an integrated circuit. Since the lateral diffusion of the dopant can be accurately controlled, narrow strips of the doped silicon can be achieved.

Method of making silicon-insulator-polysilicon infrared image device utilizing epitaxial deposition and selective etching

Abstract: A layer of epitaxial silicon is grown on a silicon growth substrate, a thin layer of silicon dioxide or other suitable insulator is grown (in the case of silicon dioxide) or deposited (for other insulators) on the epitaxial layer, and a thick layer of polysilicon is grown on the dioxide layer. The silicon growth substrate is then removed, and the epitaxial layer is etched to form islands on the insulator layer. Some of the islands are doped to form an array of infrared sensitive detectors, and a large island is doped to act as CCD region. Electrical leads are fabricated, some to provide drive and output lines for the CCDs, other to provide connections of the detectors to respective CCDs, and yet others to provide common leads for the detectors.

The characterisation of metal-thin insulator-n-p+ silicon switching devices

Abstract: 2014 Experiments are reported on the switching characteristics of MISS devices incorporating a thin ( 50 Å) oxide layer, including the influence of a modulating base current, the effect of temperature and the dynamic performance. A quantitative analysis of a regenerative model of switching is briefly described and shown to give a good account of the experimental results. REVUE DE PHYSIQUE APPLIQUÉE TOME 13, DÉCEMBRE 1978,

Invited) Physics and Device Technology of Silicon on Sapphire

Abstract: Current status of silicon on sapphire technology has been reviewed with emphasis on the following subjects: (a) economical aspects of SOS; material availability and costs, (b) physical limitation to the carrier transport phenomena in epitaxial silicon layer, (c) characterization of SOS; role of crystal defect in silicon film on the physical and electrical properties of silicon layer, (d) device characteristics of MOSFET on SOS wafer; reduction in junction capacitance, lack in the substrate bias effects etc., (e) comparison of SOS LSI with the other bulk LSI's for several basic circuit configurations.

Fabrication of very large scale integrated circuits containing N-channel silicon gate nonvolatile memory elements

Abstract: A method of fabricating very large scale integrated circuits including N-channel silicon gate nonvolatile memory elements and additional peripheral transistor elements. The nonvolatile memory elements are fabricated as PDS protected drain-source devices composed of a variable threshold memory device having a thin silicon dioxide gate insulator in combination with a pair of fixed threshold devices having a thicker silicon dioxide gate insulator arranged with a common silicon nitride layer and common gate electrode. The additional fixed threshold peripheral transistors are fabricated without a silicon nitride layer. In addition, the method contains no processing steps subsequent to the fabrication of the PDS devices which necessitate the application of temperatures in excess of 900° C.

Semiconductor memory unit

Abstract: PURPOSE:To contrive to enhance the speed of a semiconductor memory unit, and to reduce intensity of an electric field to be applied to the capacitor of the unit by a method wherein the capacitor is constructed of a first insulating layer, a semiconductor layer and a semiconductor substrate, and the semiconductor substrate is biased to the middle level potential between electric power source potential and earth potential CONSTITUTION:A first insulating layer 2 and a semiconductor layer 3 are adhered in order on a semiconductor substrate 1, a gate electrode 5 is provided on the semiconductor layer 3 interposing a second insulating layer 4 between them, and moreover a source region 3S and a drain region 3D are formed in the semiconductor layer 3 to construct a transistor, a capacitor is constructed using the first insulating layer 2 as a dielectric layer, the semiconductor layer 3 as an electrode on the storage side and the semiconductor substrate 1 as a facing electrode, and the semiconductor substrate 1 is biased to the middle level potential between electric power source potential and earth potential According to construction of SOI structure of the memory cell, action at a high speed can be attained, to apply the voltage of the middle level between electric power source potential VCC and earth potential VSS can be attained, and reliability of the thin film capacitor is enhanced

Studies of Indium-Doped Silicon

Abstract: : Areas of current interest in infrared detector development include the development of larger arrays, the use of cheaper materials, and the integration of the detectors and processing electronics onto the same chip. Silicon doped with various impurities can be used as a photodetector in many regions of the infrared. silicon is available in large areas and the technology and equipment needed to process the detectors and coupled electronics is that used in the current silicon electronics industry. Because of this the production of chips with integrated detectors and electronics would be cheaper with silicon than with any other material. The yields, uniformity, and quality of silicon devices might be expected to be better for silicon than for any other less highly developed material and the development time and cost should be much less. The specific aims of this study effort were three fold: (1) Develop a new growth process which can produce better-quality indium-doped silicon than current Czochralski or float-zone techniques; (2) Determine the origin of the X-center and if possible eliminate it, and (3) Determine the trapping parameters of centers in indium-doped silicon.

Method of making a planar semiconductor device.

Abstract: A semiconductor device (10) includes a region (32) of polycrystalline silicon on a portion of the surface (13) of a body (12) of semiconductor material. A layer (26) of oxidized polycrystalline silicon is also on the semiconductor material body and extends to the polycrystalline silicon region. The surface of the silicon oxide layer is substantially coplanar with the surface of the polycrystalline silicon region so that a metal film conductor (28) can be easily provided over the semiconductor device. The polycrystalline silicon region may be the gate of an MOS transistor or a conductive region of any type of semiconductor device. The semiconductor device is made by forming a polycrystalline silicon layer over the semiconductor material body, forming a mask on a portion of the polycrystalline silicon layer, reducing the thickness of the unmasked portion of the polycrystalline silicon layer and then oxidizing the unmasked portion of the polycrystalline silicon layer to form the oxide layer. In MOS transistors, both the contacts and gate of the device can be formed from one polycrystalline silicon layer by appropriate masking, thinning, and oxidizing steps.