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Showing papers on "Silicon on insulator published in 1983"


Journal ArticleDOI
TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Abstract: The charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI: e.g,, recrystallized Si on SiO 2 ) MOSFET's is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived. The expressions clearly show the dependence of the linear-region channel conductance on the back-gate bias and on the device parameters, including those of the back silicon-insulator interface. The analysis is supported by current-voltage measurements of laser-recrystallized SOI MOSFET's. The results suggest how the back-gate bias may be used to optimize the performance of the SOI MOSFET in particular applications.

662 citations


Journal ArticleDOI
TL;DR: In this article, the epitaxial lateral overgrowth (ELO) process is used for the growth of silicon film over an SiO2 mask by the CVD technique.

143 citations


Journal ArticleDOI
TL;DR: In this paper, a thin-film lateral n-p-n bipolar transistors with different base widths (5 and 10 µm) have been fabricated in moving melt zone recrystallized silicon on a 0.5µm silicon dioxide substrate.
Abstract: Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.

101 citations


Journal ArticleDOI
TL;DR: In this article, graphoepitaxy and zone-melting recrystallization of patterned Si films are reviewed, with emphasis on their application to silicon on insulator (SOI).

94 citations


Journal ArticleDOI
TL;DR: In this paper, a silicon wafer was implanted with 200 keV oxygen to dosss of up to 2.4 × 10 18 O + /cm 2 at implantation temperatures of 325°C to 600°C.

68 citations


Journal ArticleDOI
TL;DR: In this article, the concepts emerging from this work which are in the present author's opinion the most useful are identified and suggestions are made as to how this structure can be used to improve the present silicon cell technology.

62 citations


Journal ArticleDOI
TL;DR: In this article, the microstructure of these materials are compared and the main defects in both the laser and graphite strip heater recrystallized material are subgrain boundaries.

58 citations


Journal ArticleDOI
TL;DR: In this paper, a silicon on insulator (SOI) for VLSI applications is presented, where the insulator is a buried silicon nitride formed by nitrogen implantation and annealing.
Abstract: A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.

50 citations


Patent
12 Aug 1983
TL;DR: In this paper, a method for growing Silicon On Insulator (SOI) films using only conventional very large scale integration (VLSI) techniques is provided, by sequentially varying the flow of HCL gas during the vertical growth, lateral-overgrowth, coalescence, and planarization stages of the epitaxial deposition process.
Abstract: A method for growing Silicon On Insulator (SOI) films using only conventional very large scale integration (VLSI) techniques is provided. By sequentially varying the flow of HCL gas during the vertical-growth, lateral-overgrowth, coalescence, and planarization stages of the epitaxial deposition process allows the formation of high-quality SOI films on wider oxide stripes suitable for general transistor applications.

48 citations


Patent
14 Nov 1983
TL;DR: In this paper, the antireflective coating pattern is made up of a series of parallel stripes terminating in seeding windows, and a laser beam is scanned perpendicular to the stripes and over at least two stripes simultaneously.
Abstract: Regular arrays of grain boundary free silicon islands have been produced in a silicon on insulator (SOI) structure by using a pattern antirelfective coating in combination with a laser scanning technique. The antireflective coating pattern is made up of a series of parallel stripes terminating in seeding windows. A laser beam is scanned perpendicular to the stripes and over at least two stripes simultaneously, with the long axis of the beam parallel to the scan direction. Grain boundaries are confined to the region under the antireflective stripes.

39 citations


Journal ArticleDOI
TL;DR: In this paper, a 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length, and the chip-select access time of the RAM was 12ns at 45mW dissipation power.
Abstract: SIMOX technology has been developed for fabricating SOI-type devices. In this technology, buried silicon oxide is used for the vertical isolation of semiconductor devices. The buried oxide is formed by oxygen-ion implantation into silicon, followed by epitaxial growth of silicon onto the surface of the residual silicon above the buried oxide. The crystallinity of the residual silicon was investigated by electron beam diffraction, while the implanted oxygen depth profile was analyzed by Rutherford backscattering spectroscopy. A 1Kb CMOS static RAM has been fabricated using polysilicon gate SIMOX technology with a 1.5μm effective channel length. The chip-select access time of the RAM was 12ns at 45mW dissi-pation power.

Patent
02 May 1983
TL;DR: In this paper, a nonvolatile memory device is presented, which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions, where a gate is formed directly on a substrate of an insulative material (e.g. non-silicon material).
Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material). The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation. The recrystallized silicon is patterned into the device active area and a source and drain in alignment with the underlying gate are implanted therein.

Journal ArticleDOI
TL;DR: A silicon-on-insulator (SOI) material structure can be produced by the formation of a buried oxide layer beneath the surface of a silicon wafer by the implantation of oxygen ions.

Journal ArticleDOI
TL;DR: The most mature SOI technology other than silicon-on-sapphire is SIMOX, or Separation by Implanted Oxygen as discussed by the authors, where high energy oxygen ions are implanted into single crystal silicon until a stoichiometric buried silicon dioxide layer is formed.
Abstract: Silicon-on-Insulator structures will be an important technological advance used in future VLSI, VHSIC and threedimensional integrated circuits. The most mature SOI technology other than silicon-on-sapphire is SIMOX, or Separation by Implanted Oxygen. High energy oxygen ions are implanted into single crystal silicon until a stoichiometric buried silicon dioxide layer is formed. After implantation, the material is annealed at high temperature to remove implantation induced defects. The structure is completed by the growth of a thin epitaxial silicon layer. Devices and complex circuits have been successfully fabricated by several research groups. This paper reviews the development of this buried oxide SOI technology from 1973 to 1983. The five major sections discuss the advantages of SOI, the basics of buried oxide formation, the literature published between 1973 and 1983, key issues that must be solved before large scale implementation takes place and, finally, predictions of future developments.

Proceedings ArticleDOI
01 Jan 1983
TL;DR: In this article, a planarized heat sink (PHS) polysilicon layer was employed to eliminate the impediment to a grain growth at the steps due to a lower IC.
Abstract: Multilayer CMOS devices were fabricated by a laser recrystallization technology. The single crystalline silicon islands embedded in an insulator on the top of MOS IC were studied. To minimize the thermal influence on a lower IC during the fabrication process, a CVD-SiO 2 was used as a retaining wall of silicon islands instead of a LOCOS. In addition, a planarized heat sink (PHS) polysilicon layer was employed to eliminate the impediment to a grain growth at the steps due to a lower IC. The single crystalline silicon islands were successfully obtained. The field effect mobility of NMOS transistors fabricated on single-crystallied silicon islands was calculated as about 400 cm2/V.sec, 490cm2/V.sec. The 10 bit CMOS shift register fabricated just on a lower IC was successfully operated at V DD =6.5 V, f CLK = 1 MHz. The 4 bit CMOS shift register, stacking PMOS on NMOS was also successfully operated.

Patent
Jayant K. Bhagat1
04 Nov 1983
TL;DR: In this article, a method of forming a silicon nitride coating in situ on a silicon surface by ion milling is described, where contact areas are substantially registered with and self-aligned with functional regions.
Abstract: A method of forming a silicon nitride coating in situ on a silicon surface by ion milling. The ion milling and silicon nitride formation process are uniquely integrated in semiconductor manufacturing methods to provide several benefits, including contact areas being substantially registered with and self-aligned with functional regions.

Journal ArticleDOI
TL;DR: In this paper, a heterojunction emitter structure based on a tunneling metal-thin insulator-semiconductor (MIS) contact in conjunction with a shallow implanted base region is described.
Abstract: Silicon bipolar transistors are described with common emitter current gains approaching 25 000, believed to be the highest ever reported for a bipolar device. A heterojunction emitter structure based on a tunneling metal-thin insulator-semiconductor (MIS) contact in conjunction with a shallow implanted base region is responsible for this improved performance. The significance of this result lies in the fact that it demonstrates advantages in both the injection efficiency of the emitter and the control of base properties which may lead to improved silicon bipolar transistor performance over a range of applications.

Journal ArticleDOI
Jean-Pierre Colinge1, E. Demoulin1, D. Bensahel1, G. Auvert1, H. Morel1 
TL;DR: In this article, a capping layer of patterned antireflecting stripes of Si 3 N 4 was used to grow large single-crystals of silicon, which showed good electrical characteristics and a surface mobility up to 650 cm2/V.s for electrons.
Abstract: Test transistors with gate lengths ranging from 10 to 4 µm were made in laser-recrystallized silicon on insulator films. A capping layer of patterned antireflecting stripes of Si 3 N 4 was used to grow large single-crystals of silicon. MOS transistors show good electrical characteristics and a surface mobility up to 650 cm2/V.s for electrons. With the exception of the recrystallization procedure, the wafers followed a fully standard NMOS process, including the growth of a LOCOS field oxide.

Journal ArticleDOI
TL;DR: In this article, the authors report experiments to depth profile these layered structures by SIMS and show that prolonged high temperature annealing leads to diffusion of oxygen with the formation of a denuded layer of thickness 1000-1500 A which is of a suitable quality for successful fabrication of high performance MOS devices.

Patent
29 Dec 1983
TL;DR: In this paper, the authors proposed to make the direction of the grain boundary parallel to a direction of channels in an SOI substrate to obtain high-speed MOSFET.
Abstract: PURPOSE:To obtain the titled device in which a shift register or the like comprises the sufficient high-speed performance by using an SOI substrate by making a channel direction of MOS type elements the direction of a grain boundary of a semiconductor layer substantially. CONSTITUTION:If a crystallization direction of laser is made parallel to a direction of channels in an SOI substrate, an abnormal diffusion layer 7 of impurity is formed along a grain boundary 6 when a source and drain junction 5 is formed. Accordingly, the source and drain junction 5 tends to be shorten and the possible minimum channel length is about 5mum. For MOSFET10 of a matrix type liquid crystal display device, the predetermind switching function for applying a voltage to a liquid crystal 11 and holding it is necessary. The characteristics of the MOSFET fabricated by SOI technique almost satisfy this function. The switching element used for a liquid crystal display element enables the channel length of 3-5mum or above. Namely, the practical and high-speed matrix type semiconductor device fabricated by SOI technique becomes possible by making a direction of the grain boundary parallel to a direction of the channels.

Journal ArticleDOI
TL;DR: In this paper, the authors propose the use of structured copper which is made of many separate copper wires and can he directly attached to silicon without introducing large stresses, and present methods of preparing structured copper along with some examples of its application.
Abstract: The large difference in thermal expansion between silicon and the high conductivity metals is a major problem to be solved in the packaging of high power silicon devices. One solution is by the use of structured copper which is made of many separate copper wires and can he directly attached to silicon without introducing large stresses. Methods of preparing structured copper are presented along with some examples of its application.

Journal ArticleDOI
Jean-Pierre Colinge1, D. Bensahel1, M. Alamome1, M. Haond1, J.C. Pfister1 
TL;DR: In this paper, a technique combining a raster laser scan, selective annealing using patterned antireflection stripes and a seeding window has been successfully used to grow large single crystals of silicon-on-insulator.
Abstract: A technique combining a raster laser scan, selective annealing using patterned antireflection stripes and a seeding window has been successfully used to grow large single crystals of silicon-on-insulator. The raster-scanned laser spot simulates an advancing linear heat source and the anti-reflection stripes modulate the trailing edge in such a way that parasitic random nucleation is avoided. The seeding gives the film its crystal orientation.

Patent
23 Dec 1983
TL;DR: In this article, an n-type silicon carbide single crystal film and a p-n junction diode are grown on an n type silicon single crystal substrate by CVD method and mesa etching is done to remove the peripheral part.
Abstract: PURPOSE:To enable manufacture of silicon carbide semiconductor elements suitable for mass production on an industrial scale with considering productivity by using a silicon carbide single crystal film grown on a silicon single crystal substrate. CONSTITUTION:An n type silicon carbide single crystal film 2 and a p type silicon carbide single crystal film 3 are grown on an n type silicon single crystal substrate 1 by CVD method and mesa etching is done to remove the peripheral part. Ni is stuck as an ohmic electrode 4 by plating and Al-Si alloy is vapor- deposited as an ohmic electrode 5. Lead wires are connected to the electrodes 4 and 5 to fabricate a p-n junction diode.

Journal ArticleDOI
TL;DR: In this paper, the selective annealing technique (LASN under patterned antireflecting coating) has been successfully applied to the growth of very large (20 µm × 3000 µm) silicon single crystals.
Abstract: The selective annealing technique (laser annealing under patterned antireflecting coating) has been successfully applied to the growth of very large (20 µm × 3000 µm) silicon single crystals. The grain boundary location is controlled by a conventional lithography step, and the grains obtained have a nearly perfect rectangular shape.

Patent
25 Aug 1983
TL;DR: In this article, a process for forming a single crystal silicon layer by heating a wafer, which is made of a single-crystal silicon substrate and a starting silicon layer made of amorphous or polycrystalline silicon and provided on the silicon substrate, is described.
Abstract: Disclosed herein is a process for forming a single crystal silicon layer by heating a wafer, which is made of a single crystal silicon substrate and a starting silicon layer made of amorphous or polycrystalline silicon and provided on the silicon substrate, in accordance with the epitaxial growth technique. The process comprises providing a heat source which is formed of a plurality of tubular lamps provided side by side with their longitudinal axes extending substantially in parallel with one another in a second plane lying above and substantially in parallel with a first plane--in which the wafer is placed--and a tubular melting-lamp provided at a position between the first and second planes and with its longitudinal axis substantially in parallel with the longitudinal axes of the tubular lamps in the second plane; and moving the wafer in the first plane and in a direction perpendicular to the longitudinal axes of the plurality of tubular lamps and that of the tubular melting-lamp in a state that all the tubular lamps of the heat source, including the tubular melting-lamp, are lit on. The above process can convert the starting silicon layer in its entirety into a single crystal silicon layer in a relatively short period of time and without danger of damaging the wafer. The above process facilitates formation of single crystal silicon layers which make up SOI structures.

Journal ArticleDOI
TL;DR: In this paper, the authors reviewed the metal-insulator-semiconductor structure of silicon solar cells and showed that neither of these conditions will be satisfied in the near or intermediate term, and the spray deposition of conductive oxide semiconductors seems to be most promising for large-scale production.

Journal ArticleDOI
Yamichi Ohmura1, Kenji Shibata1, T. Inoue1, T. Yoshii1, Y. Horiike1 
TL;DR: In this article, a 25-stage n-MOS ring oscillator with a fan out of one composed of 4-µm transistors was successfully fabricated in CW electron-beam recrystallized polysilicon/Si 3 N 4 /SiO 2 /
Abstract: Both 25-stage n-MOS enhancement driver/enhancement load (E/E) and enhancement driver/depletion load (E/D) ring oscillators with a fan out of one composed of 4-µm channel length transistors have been successfully fabricated in CW electron-beam recrystallized polysilicon/Si 3 N 4 /SiO 2 /

Proceedings ArticleDOI
H.W. Lam1
01 Jan 1983
TL;DR: In this article, the progress of beam-recrystallized SOI, implanted buried oxide and full isolation by Porous Oxidized Silicon is summarized in terms of performance and cost.
Abstract: Silicon-on-Insulator (SOI) technologies are becoming more important as CMOS becomes the preferred technology for VLSI. The progress of the three most actively researched SOI technologies, beam-recrystallized SOI, implanted buried oxide and Full Isolation by Porous Oxidized Silicon will be summarized in this paper.


Patent
Lorenzo Faraone1
01 Sep 1983
TL;DR: In this paper, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.
Abstract: A method of making a semiconductor device having multi-levels of polycrystalline silicon conductors insulated from each other and from the silicon substrate on which the semiconductor device if formed. In this method, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.